futilehdl/src/frontend.rs

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use std::collections::BTreeMap;
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use crate::builtin_cells::get_builtins;
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use crate::parser;
use crate::rtlil;
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use crate::rtlil::RtlilWrite;
pub use callable::Callable;
pub use types::{Type, TypeStruct};
mod callable;
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pub mod typed_ir;
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pub mod types;
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/// lots of code is still not width-aware, this constant keeps track of that
const TODO_WIDTH: u32 = 1;
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fn make_pubid(id: &str) -> String {
"\\".to_owned() + id
}
#[derive(Debug)]
pub enum CompileErrorKind {
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UndefinedReference(String),
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BadArgCount { received: usize, expected: usize },
}
#[derive(Debug)]
pub struct CompileError {
kind: CompileErrorKind,
}
impl CompileError {
fn new(kind: CompileErrorKind) -> Self {
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Self { kind }
}
}
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/// A user-defined signal
pub struct Signal<'ctx> {
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/// the user-visible name of the signal
pub name: String,
/// the id of the signal in RTLIL
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pub il_id: String,
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/// the type of the signal
pub typ: Type<'ctx>,
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// unique ID of the signal
// pub uid: u64,
}
impl<'ctx> Signal<'ctx> {
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fn sigspec(&self) -> rtlil::SigSpec {
rtlil::SigSpec::Wire(self.il_id.to_owned())
}
}
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/// context used when generating processes
struct ProcContext {
updates: Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
next_sigs: BTreeMap<String, rtlil::SigSpec>,
}
struct Context<'ctx> {
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/// map callable name to callable
callables: BTreeMap<String, Callable<'ctx>>,
/// types
types: Vec<TypeStruct<'ctx>>,
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/// map signal name to Signal
signals: BTreeMap<String, Signal<'ctx>>,
}
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impl<'ctx> Context<'ctx> {
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fn get_signal(&self, signame: &str) -> Option<&Signal> {
self.signals.get(signame)
}
fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
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self.get_signal(signame).ok_or_else(|| {
CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned()))
})
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}
}
fn lower_process_statement(
ctx: &Context,
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pctx: &mut ProcContext,
module: &mut rtlil::Module,
stmt: &parser::proc::ProcStatement,
) -> Result<rtlil::CaseRule, CompileError> {
let rule = match stmt {
parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
parser::proc::ProcStatement::Assign(assig) => {
// FIXME: actually store this
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let next_sig;
if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
next_sig = sig.clone();
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} else {
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let next_gen_id = format!("${}$next", assig.lhs);
module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
next_sig = rtlil::SigSpec::Wire(next_gen_id);
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pctx.next_sigs
.insert(assig.lhs.to_owned(), next_sig.clone());
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// trigger the modified value to update
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pctx.updates
.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
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};
let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
rtlil::CaseRule {
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assign: vec![(next_sig, next_expr_wire)],
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switches: vec![],
}
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}
parser::proc::ProcStatement::Match(match_block) => {
let match_sig = lower_expression(ctx, module, &match_block.expr)?;
let mut cases = vec![];
for arm in &match_block.arms {
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let case = lower_process_statement(ctx, pctx, module, &arm.1)?;
let compare_sig = lower_expression(ctx, module, &arm.0)?;
cases.push((compare_sig, case));
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}
let switch_rule = rtlil::SwitchRule {
signal: match_sig,
cases,
};
rtlil::CaseRule {
assign: vec![],
switches: vec![switch_rule],
}
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}
parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
};
Ok(rule)
}
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fn lower_process(
ctx: &Context,
module: &mut rtlil::Module,
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process: &parser::proc::ProcBlock,
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) -> Result<(), CompileError> {
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let mut pctx = ProcContext {
updates: vec![],
next_sigs: BTreeMap::new(),
};
let mut cases = vec![];
for stmt in &process.items {
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let case = lower_process_statement(ctx, &mut pctx, module, stmt)?;
cases.push(case);
}
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let sync_sig = ctx.try_get_signal(process.net.fragment())?;
let sync_cond = rtlil::SyncCond::Posedge(sync_sig.sigspec());
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let sync_rule = rtlil::SyncRule {
cond: sync_cond,
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assign: pctx.updates,
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};
if cases.len() != 1 {
panic!("only one expression per block, for now")
}
assert_eq!(cases.len(), 1);
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let ir_proc = rtlil::Process {
id: module.make_genid("proc"),
root_case: cases.into_iter().next().unwrap(),
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sync_rules: vec![sync_rule],
};
module.add_process(ir_proc);
Ok(())
}
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fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
match op {
parser::Operation::And { a, b } => {
let a = desugar_expression(a);
let b = desugar_expression(b);
parser::Call {
name: "and".into(),
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args: vec![a, b],
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}
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}
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parser::Operation::Or { a, b } => {
let a = desugar_expression(a);
let b = desugar_expression(b);
parser::Call {
name: "or".into(),
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args: vec![a, b],
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}
}
parser::Operation::Xor { a, b } => {
let a = desugar_expression(a);
let b = desugar_expression(b);
parser::Call {
name: "xor".into(),
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args: vec![a, b],
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}
}
parser::Operation::Not(a) => {
let a = desugar_expression(a);
parser::Call {
name: "not".into(),
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args: vec![a],
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}
}
}
}
fn desugar_expression<'a>(expr: parser::Expression<'a>) -> parser::Expression<'a> {
// TODO: allow ergonomic traversal of AST
match expr {
parser::Expression::Ident(_) => expr,
parser::Expression::Literal(_) => expr,
parser::Expression::Call(mut call) => {
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let new_args = call.args.into_iter().map(desugar_expression).collect();
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call.args = new_args;
parser::Expression::Call(call)
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}
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parser::Expression::Operation(op) => {
parser::Expression::Call(Box::new(desugar_operation(*op)))
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}
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}
}
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fn lower_expression(
ctx: &Context,
module: &mut rtlil::Module,
expr: &parser::Expression,
) -> Result<rtlil::SigSpec, CompileError> {
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let expr = desugar_expression(expr.clone());
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match expr {
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parser::Expression::Ident(ident) => {
let signal = ctx.try_get_signal(ident)?;
Ok(signal.sigspec())
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}
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parser::Expression::Call(call) => {
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let args_resolved = call
.args
.iter()
.map(|expr| lower_expression(ctx, module, expr))
.collect::<Result<Vec<_>, _>>()?;
let callable = ctx
.callables
.get(call.name.fragment() as &str)
.ok_or_else(|| {
CompileError::new(CompileErrorKind::UndefinedReference(
call.name.fragment().to_string(),
))
})?;
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if args_resolved.len() != callable.argcount() {
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
expected: callable.argcount(),
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received: args_resolved.len(),
}));
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}
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let cell_id = module.make_genid(callable.name());
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let output_gen_id = format!("{}$out", &cell_id);
module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
// let cell =
// (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
// module.add_cell(cell);
Ok(output_gen_wire)
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}
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// TODO: instantiate operators directly here instead of desugaring, once the callable infrastructure improves
// to get better errors
parser::Expression::Operation(_op) => todo!("operators not yet implemented"),
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parser::Expression::Literal(lit) => Ok(rtlil::SigSpec::Const(lit as i64, TODO_WIDTH)),
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}
}
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fn lower_assignment(
ctx: &Context,
module: &mut rtlil::Module,
assignment: parser::Assign,
) -> Result<(), CompileError> {
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let target_id = ctx.try_get_signal(assignment.lhs)?.sigspec();
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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module.add_connection(&target_id, &return_wire);
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Ok(())
}
pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name.fragment()));
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let mut context = Context {
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callables: get_builtins()
.into_iter()
.map(|clb| (clb.name().to_owned(), clb))
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.collect(),
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signals: BTreeMap::new(),
types: vec![],
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};
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writer.write_line("autoidx 1");
for (idx, port) in pa_module.ports.iter().enumerate() {
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// FIXME: Actually resolve types
let sigtype = TypeStruct::logic_width(TODO_WIDTH);
// FIXME: CRIMES CRIMES CRIMES
let sigtype = Box::leak(Box::new(sigtype));
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let sig = Signal {
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name: port.net.name.fragment().to_string(),
il_id: make_pubid(port.net.name.fragment()),
typ: sigtype,
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};
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let sig = context
.signals
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.entry(port.net.name.fragment().to_string())
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.or_insert(sig);
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let dir_option = match port.direction {
parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
};
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let wire = rtlil::Wire::new(sig.il_id.to_owned(), TODO_WIDTH, Some(dir_option));
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ir_module.add_wire(wire);
}
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for item in pa_module.items {
match item {
parser::ModuleItem::Assign(assignment) => {
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lower_assignment(&context, &mut ir_module, assignment)?
}
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parser::ModuleItem::Proc(proc) => lower_process(&context, &mut ir_module, &proc)?,
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}
}
ir_module.write_rtlil(&mut writer);
Ok(writer.finish())
}