2022-01-05 01:08:25 +00:00
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use std::collections::BTreeMap;
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2022-01-05 01:09:08 +00:00
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use crate::builtin_cells::get_builtins;
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2022-01-04 22:05:25 +00:00
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use crate::parser;
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use crate::rtlil;
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2022-01-16 18:11:56 +00:00
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use crate::rtlil::RtlilWrite;
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2022-01-23 20:04:19 +00:00
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pub use callable::Callable;
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pub use types::{Type, TypeStruct};
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mod callable;
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2022-01-30 22:54:19 +00:00
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pub mod typed_ir;
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2022-02-01 18:46:06 +00:00
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pub mod types;
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2022-01-04 22:05:25 +00:00
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2022-01-17 14:37:07 +00:00
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/// lots of code is still not width-aware, this constant keeps track of that
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const TODO_WIDTH: u32 = 1;
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2022-01-04 22:05:25 +00:00
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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}
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#[derive(Debug)]
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2022-01-04 23:13:56 +00:00
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pub enum CompileErrorKind {
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2022-01-05 01:09:08 +00:00
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UndefinedReference(String),
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2022-01-14 14:32:00 +00:00
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BadArgCount { received: usize, expected: usize },
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2022-01-04 23:13:56 +00:00
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}
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#[derive(Debug)]
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pub struct CompileError {
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kind: CompileErrorKind,
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}
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impl CompileError {
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fn new(kind: CompileErrorKind) -> Self {
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2022-01-05 01:09:08 +00:00
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Self { kind }
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2022-01-04 23:13:56 +00:00
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}
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}
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2022-01-17 20:02:11 +00:00
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/// A user-defined signal
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2022-01-23 20:04:19 +00:00
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pub struct Signal<'ctx> {
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2022-01-17 20:02:11 +00:00
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/// the user-visible name of the signal
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pub name: String,
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/// the id of the signal in RTLIL
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2022-01-17 20:04:22 +00:00
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pub il_id: String,
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2022-01-17 20:02:11 +00:00
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/// the type of the signal
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2022-01-23 20:04:19 +00:00
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pub typ: Type<'ctx>,
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2022-01-17 20:02:11 +00:00
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// unique ID of the signal
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// pub uid: u64,
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}
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2022-01-23 20:04:19 +00:00
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impl<'ctx> Signal<'ctx> {
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2022-01-17 20:04:22 +00:00
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fn sigspec(&self) -> rtlil::SigSpec {
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rtlil::SigSpec::Wire(self.il_id.to_owned())
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}
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}
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2022-01-17 23:11:37 +00:00
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/// context used when generating processes
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struct ProcContext {
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updates: Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
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next_sigs: BTreeMap<String, rtlil::SigSpec>,
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}
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2022-01-23 20:04:19 +00:00
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struct Context<'ctx> {
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2022-01-17 20:02:11 +00:00
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/// map callable name to callable
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2022-01-23 20:04:19 +00:00
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callables: BTreeMap<String, Callable<'ctx>>,
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/// types
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types: Vec<TypeStruct<'ctx>>,
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2022-01-17 20:02:11 +00:00
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/// map signal name to Signal
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2022-01-23 20:04:19 +00:00
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signals: BTreeMap<String, Signal<'ctx>>,
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}
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2022-01-23 20:04:19 +00:00
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impl<'ctx> Context<'ctx> {
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2022-01-17 20:04:22 +00:00
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fn get_signal(&self, signame: &str) -> Option<&Signal> {
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self.signals.get(signame)
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}
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fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
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2022-01-20 18:55:17 +00:00
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self.get_signal(signame).ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned()))
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})
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2022-01-17 20:04:22 +00:00
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}
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}
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2022-01-17 14:37:07 +00:00
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fn lower_process_statement(
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ctx: &Context,
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2022-01-17 23:11:37 +00:00
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pctx: &mut ProcContext,
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2022-01-17 14:37:07 +00:00
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module: &mut rtlil::Module,
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stmt: &parser::proc::ProcStatement,
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) -> Result<rtlil::CaseRule, CompileError> {
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let rule = match stmt {
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parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
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parser::proc::ProcStatement::Assign(assig) => {
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// FIXME: actually store this
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2022-01-17 23:11:37 +00:00
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let next_sig;
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if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
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next_sig = sig.clone();
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2022-01-20 18:55:17 +00:00
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} else {
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let next_gen_id = format!("${}$next", assig.lhs);
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
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next_sig = rtlil::SigSpec::Wire(next_gen_id);
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2022-01-20 18:55:17 +00:00
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pctx.next_sigs
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.insert(assig.lhs.to_owned(), next_sig.clone());
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2022-01-17 23:11:37 +00:00
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// trigger the modified value to update
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2022-01-20 18:55:17 +00:00
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pctx.updates
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.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
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2022-01-17 23:11:37 +00:00
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};
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2022-01-17 14:37:07 +00:00
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
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rtlil::CaseRule {
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2022-01-20 18:51:09 +00:00
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assign: vec![(next_sig, next_expr_wire)],
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2022-01-17 16:37:15 +00:00
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switches: vec![],
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2022-01-17 14:37:07 +00:00
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}
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2022-01-17 16:37:15 +00:00
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}
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2022-01-17 14:37:07 +00:00
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parser::proc::ProcStatement::Match(match_block) => {
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let match_sig = lower_expression(ctx, module, &match_block.expr)?;
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let mut cases = vec![];
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for arm in &match_block.arms {
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2022-01-17 23:11:37 +00:00
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let case = lower_process_statement(ctx, pctx, module, &arm.1)?;
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2022-01-17 14:37:07 +00:00
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let compare_sig = lower_expression(ctx, module, &arm.0)?;
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cases.push((compare_sig, case));
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2022-01-17 16:37:15 +00:00
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}
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2022-01-17 14:37:07 +00:00
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let switch_rule = rtlil::SwitchRule {
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signal: match_sig,
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cases,
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};
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rtlil::CaseRule {
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assign: vec![],
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switches: vec![switch_rule],
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}
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2022-01-17 16:37:15 +00:00
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}
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2022-01-17 14:37:07 +00:00
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parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
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};
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Ok(rule)
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}
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2022-01-17 00:15:27 +00:00
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fn lower_process(
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ctx: &Context,
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module: &mut rtlil::Module,
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2022-01-17 16:37:15 +00:00
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process: &parser::proc::ProcBlock,
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2022-01-17 00:15:27 +00:00
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) -> Result<(), CompileError> {
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2022-01-17 23:11:37 +00:00
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let mut pctx = ProcContext {
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updates: vec![],
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next_sigs: BTreeMap::new(),
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};
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2022-01-17 14:37:07 +00:00
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let mut cases = vec![];
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for stmt in &process.items {
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2022-01-17 23:11:37 +00:00
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let case = lower_process_statement(ctx, &mut pctx, module, stmt)?;
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2022-01-17 14:37:07 +00:00
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cases.push(case);
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}
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2022-01-17 23:11:37 +00:00
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let sync_sig = ctx.try_get_signal(process.net.fragment())?;
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let sync_cond = rtlil::SyncCond::Posedge(sync_sig.sigspec());
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2022-01-17 00:15:27 +00:00
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let sync_rule = rtlil::SyncRule {
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cond: sync_cond,
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2022-01-17 23:11:37 +00:00
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assign: pctx.updates,
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2022-01-17 00:15:27 +00:00
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};
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2022-01-17 14:37:07 +00:00
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if cases.len() != 1 {
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panic!("only one expression per block, for now")
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}
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assert_eq!(cases.len(), 1);
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2022-01-17 00:15:27 +00:00
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let ir_proc = rtlil::Process {
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id: module.make_genid("proc"),
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2022-01-17 14:37:07 +00:00
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root_case: cases.into_iter().next().unwrap(),
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2022-01-17 00:15:27 +00:00
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sync_rules: vec![sync_rule],
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};
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module.add_process(ir_proc);
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Ok(())
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}
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2022-01-17 18:20:51 +00:00
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fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
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match op {
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parser::Operation::And { a, b } => {
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let a = desugar_expression(a);
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let b = desugar_expression(b);
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parser::Call {
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name: "and".into(),
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2022-01-20 18:55:17 +00:00
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args: vec![a, b],
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2022-01-17 18:20:51 +00:00
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}
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2022-01-20 18:55:17 +00:00
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}
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2022-01-17 18:20:51 +00:00
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parser::Operation::Or { a, b } => {
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let a = desugar_expression(a);
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let b = desugar_expression(b);
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parser::Call {
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name: "or".into(),
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2022-01-20 18:55:17 +00:00
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args: vec![a, b],
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2022-01-17 18:20:51 +00:00
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}
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}
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parser::Operation::Xor { a, b } => {
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let a = desugar_expression(a);
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let b = desugar_expression(b);
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parser::Call {
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name: "xor".into(),
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2022-01-20 18:55:17 +00:00
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args: vec![a, b],
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2022-01-17 18:20:51 +00:00
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}
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}
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parser::Operation::Not(a) => {
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let a = desugar_expression(a);
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parser::Call {
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name: "not".into(),
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2022-01-20 18:55:17 +00:00
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args: vec![a],
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2022-01-17 18:20:51 +00:00
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}
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}
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}
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}
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fn desugar_expression<'a>(expr: parser::Expression<'a>) -> parser::Expression<'a> {
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// TODO: allow ergonomic traversal of AST
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match expr {
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parser::Expression::Ident(_) => expr,
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parser::Expression::Literal(_) => expr,
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parser::Expression::Call(mut call) => {
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2022-01-20 18:51:09 +00:00
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let new_args = call.args.into_iter().map(desugar_expression).collect();
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2022-01-17 18:20:51 +00:00
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call.args = new_args;
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parser::Expression::Call(call)
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2022-01-20 18:55:17 +00:00
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}
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2022-01-17 18:20:51 +00:00
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parser::Expression::Operation(op) => {
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parser::Expression::Call(Box::new(desugar_operation(*op)))
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2022-01-20 18:55:17 +00:00
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}
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2022-01-17 18:20:51 +00:00
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}
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}
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2022-01-05 01:09:08 +00:00
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fn lower_expression(
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ctx: &Context,
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module: &mut rtlil::Module,
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expr: &parser::Expression,
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2022-01-17 14:37:07 +00:00
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) -> Result<rtlil::SigSpec, CompileError> {
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2022-01-17 18:20:51 +00:00
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let expr = desugar_expression(expr.clone());
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2022-01-04 22:05:25 +00:00
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match expr {
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2022-01-17 20:04:22 +00:00
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parser::Expression::Ident(ident) => {
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let signal = ctx.try_get_signal(ident)?;
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Ok(signal.sigspec())
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2022-01-20 18:55:17 +00:00
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}
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2022-01-04 22:05:25 +00:00
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parser::Expression::Call(call) => {
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2022-01-05 01:09:08 +00:00
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let args_resolved = call
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.args
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.iter()
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.map(|expr| lower_expression(ctx, module, expr))
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.collect::<Result<Vec<_>, _>>()?;
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let callable = ctx
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.callables
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.get(call.name.fragment() as &str)
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.ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(
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call.name.fragment().to_string(),
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))
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})?;
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2022-01-05 01:08:25 +00:00
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2022-01-23 20:04:19 +00:00
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if args_resolved.len() != callable.argcount() {
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2022-01-14 14:32:00 +00:00
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
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2022-01-23 20:04:19 +00:00
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expected: callable.argcount(),
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2022-01-14 14:32:00 +00:00
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received: args_resolved.len(),
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}));
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2022-01-05 01:38:56 +00:00
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}
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2022-02-02 00:03:03 +00:00
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let cell_id = module.make_genid(callable.name());
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2022-01-05 01:08:25 +00:00
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2022-01-17 14:37:07 +00:00
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let output_gen_id = format!("{}$out", &cell_id);
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module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
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let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
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2022-01-23 20:04:19 +00:00
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// let cell =
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// (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
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// module.add_cell(cell);
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2022-01-17 14:37:07 +00:00
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Ok(output_gen_wire)
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2022-01-04 22:05:25 +00:00
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}
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2022-01-17 18:20:51 +00:00
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// TODO: instantiate operators directly here instead of desugaring, once the callable infrastructure improves
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// to get better errors
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2022-01-17 14:37:07 +00:00
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parser::Expression::Operation(_op) => todo!("operators not yet implemented"),
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2022-01-17 18:20:51 +00:00
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parser::Expression::Literal(lit) => Ok(rtlil::SigSpec::Const(lit as i64, TODO_WIDTH)),
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2022-01-04 22:05:25 +00:00
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}
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}
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2022-01-05 01:09:08 +00:00
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fn lower_assignment(
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ctx: &Context,
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module: &mut rtlil::Module,
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assignment: parser::Assign,
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) -> Result<(), CompileError> {
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2022-01-17 20:04:22 +00:00
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let target_id = ctx.try_get_signal(assignment.lhs)?.sigspec();
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2022-01-05 01:08:25 +00:00
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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2022-01-16 19:13:04 +00:00
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module.add_connection(&target_id, &return_wire);
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2022-01-04 22:05:25 +00:00
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Ok(())
|
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}
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|
|
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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|
|
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let mut writer = rtlil::ILWriter::new();
|
2022-01-23 23:10:09 +00:00
|
|
|
let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name.fragment()));
|
2022-01-17 20:02:11 +00:00
|
|
|
let mut context = Context {
|
2022-01-05 01:09:08 +00:00
|
|
|
callables: get_builtins()
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|
|
|
.into_iter()
|
2022-01-23 20:04:19 +00:00
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|
.map(|clb| (clb.name().to_owned(), clb))
|
2022-01-05 01:09:08 +00:00
|
|
|
.collect(),
|
2022-01-17 20:02:11 +00:00
|
|
|
signals: BTreeMap::new(),
|
2022-01-23 20:04:19 +00:00
|
|
|
types: vec![],
|
2022-01-05 01:09:08 +00:00
|
|
|
};
|
2022-01-23 20:04:19 +00:00
|
|
|
|
2022-01-04 22:05:25 +00:00
|
|
|
writer.write_line("autoidx 1");
|
|
|
|
for (idx, port) in pa_module.ports.iter().enumerate() {
|
2022-01-23 23:10:09 +00:00
|
|
|
// FIXME: Actually resolve types
|
|
|
|
let sigtype = TypeStruct::logic_width(TODO_WIDTH);
|
2022-01-23 20:04:19 +00:00
|
|
|
// FIXME: CRIMES CRIMES CRIMES
|
|
|
|
let sigtype = Box::leak(Box::new(sigtype));
|
2022-01-17 20:04:22 +00:00
|
|
|
let sig = Signal {
|
2022-01-23 23:10:09 +00:00
|
|
|
name: port.net.name.fragment().to_string(),
|
|
|
|
il_id: make_pubid(port.net.name.fragment()),
|
2022-01-23 20:04:19 +00:00
|
|
|
typ: sigtype,
|
2022-01-17 20:04:22 +00:00
|
|
|
};
|
2022-01-20 18:55:17 +00:00
|
|
|
let sig = context
|
|
|
|
.signals
|
2022-01-23 23:10:09 +00:00
|
|
|
.entry(port.net.name.fragment().to_string())
|
2022-01-20 18:55:17 +00:00
|
|
|
.or_insert(sig);
|
2022-01-17 20:04:22 +00:00
|
|
|
|
2022-01-04 22:05:25 +00:00
|
|
|
let dir_option = match port.direction {
|
|
|
|
parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
|
|
|
|
parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
|
|
|
|
};
|
2022-02-01 18:46:06 +00:00
|
|
|
let wire = rtlil::Wire::new(sig.il_id.to_owned(), TODO_WIDTH, Some(dir_option));
|
2022-01-04 22:05:25 +00:00
|
|
|
ir_module.add_wire(wire);
|
|
|
|
}
|
2022-01-16 20:46:44 +00:00
|
|
|
for item in pa_module.items {
|
|
|
|
match item {
|
|
|
|
parser::ModuleItem::Assign(assignment) => {
|
2022-01-05 01:09:08 +00:00
|
|
|
lower_assignment(&context, &mut ir_module, assignment)?
|
|
|
|
}
|
2022-01-17 16:37:15 +00:00
|
|
|
parser::ModuleItem::Proc(proc) => lower_process(&context, &mut ir_module, &proc)?,
|
2022-01-04 22:05:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
ir_module.write_rtlil(&mut writer);
|
|
|
|
Ok(writer.finish())
|
|
|
|
}
|