futilehdl/src/frontend.rs

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use std::collections::BTreeMap;
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use crate::builtin_cells::get_builtins;
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use crate::parser;
use crate::rtlil;
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use crate::rtlil::RtlilWrite;
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fn make_pubid(id: &str) -> String {
"\\".to_owned() + id
}
#[derive(Debug)]
pub enum CompileErrorKind {
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UndefinedReference(String),
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BadArgCount { received: usize, expected: usize },
}
#[derive(Debug)]
pub struct CompileError {
kind: CompileErrorKind,
}
impl CompileError {
fn new(kind: CompileErrorKind) -> Self {
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Self { kind }
}
}
pub enum GenericParam<T> {
Unsolved,
Solved(T),
}
pub enum Type {
/// a wire of some width
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Wire(GenericParam<u32>),
}
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impl Type {
pub fn wire() -> Self {
Self::Wire(GenericParam::Unsolved)
}
}
pub struct CallArgument {
pub name: String,
pub atype: Type,
}
// module that can be instantiated like a function
pub struct Callable {
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pub name: String,
pub args: Vec<CallArgument>,
pub ret: Type,
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pub instantiate: Box<dyn Fn(&str, &[String], &str) -> rtlil::Cell>,
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}
struct Context {
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callables: BTreeMap<String, Callable>,
}
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fn lower_expression(
ctx: &Context,
module: &mut rtlil::Module,
expr: &parser::Expression,
) -> Result<String, CompileError> {
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match expr {
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parser::Expression::Ident(ident) => Ok(make_pubid(ident)),
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parser::Expression::Call(call) => {
let output_gen_id = module.make_genid("cell");
module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None));
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let args_resolved = call
.args
.iter()
.map(|expr| lower_expression(ctx, module, expr))
.collect::<Result<Vec<_>, _>>()?;
let callable = ctx
.callables
.get(call.name.fragment() as &str)
.ok_or_else(|| {
CompileError::new(CompileErrorKind::UndefinedReference(
call.name.fragment().to_string(),
))
})?;
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if args_resolved.len() != callable.args.len() {
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
expected: callable.args.len(),
received: args_resolved.len(),
}));
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}
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let cell_id = module.make_genid(&callable.name);
let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_id);
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module.add_cell(cell);
Ok(output_gen_id)
}
parser::Expression::Operation(_op) => todo!(),
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}
}
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fn lower_assignment(
ctx: &Context,
module: &mut rtlil::Module,
assignment: parser::Assign,
) -> Result<(), CompileError> {
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let target_id = make_pubid(assignment.lhs);
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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module.add_connection(&target_id, &return_wire);
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Ok(())
}
pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name));
let context = Context {
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callables: get_builtins()
.into_iter()
.map(|clb| (clb.name.to_owned(), clb))
.collect(),
};
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writer.write_line("autoidx 1");
for (idx, port) in pa_module.ports.iter().enumerate() {
let dir_option = match port.direction {
parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
};
let wire = rtlil::Wire::new(
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make_pubid(port.net.name),
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port.net.width.unwrap_or(1) as u32,
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Some(dir_option),
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);
ir_module.add_wire(wire);
}
for stmt in pa_module.statements {
match stmt {
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parser::Statement::Assign(assignment) => {
lower_assignment(&context, &mut ir_module, assignment)?
}
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}
}
ir_module.write_rtlil(&mut writer);
Ok(writer.finish())
}