futilehdl/src/frontend.rs

235 lines
7.1 KiB
Rust
Raw Normal View History

2022-01-05 01:08:25 +00:00
use std::collections::BTreeMap;
2022-01-05 01:09:08 +00:00
use crate::builtin_cells::get_builtins;
2022-01-04 22:05:25 +00:00
use crate::parser;
use crate::rtlil;
2022-01-16 18:11:56 +00:00
use crate::rtlil::RtlilWrite;
2022-01-04 22:05:25 +00:00
/// lots of code is still not width-aware, this constant keeps track of that
const TODO_WIDTH: u32 = 1;
2022-01-04 22:05:25 +00:00
fn make_pubid(id: &str) -> String {
"\\".to_owned() + id
}
#[derive(Debug)]
pub enum CompileErrorKind {
2022-01-05 01:09:08 +00:00
UndefinedReference(String),
2022-01-14 14:32:00 +00:00
BadArgCount { received: usize, expected: usize },
}
#[derive(Debug)]
pub struct CompileError {
kind: CompileErrorKind,
}
impl CompileError {
fn new(kind: CompileErrorKind) -> Self {
2022-01-05 01:09:08 +00:00
Self { kind }
}
}
pub enum GenericParam<T> {
Unsolved,
Solved(T),
}
pub enum Type {
/// a wire of some width
2022-01-05 01:09:08 +00:00
Wire(GenericParam<u32>),
}
2022-01-05 01:08:25 +00:00
impl Type {
pub fn wire() -> Self {
Self::Wire(GenericParam::Unsolved)
}
}
pub struct CallArgument {
pub name: String,
pub atype: Type,
}
// module that can be instantiated like a function
pub struct Callable {
2022-01-05 01:08:25 +00:00
pub name: String,
pub args: Vec<CallArgument>,
pub ret: Type,
pub instantiate: Box<dyn Fn(&str, &[rtlil::SigSpec], &rtlil::SigSpec) -> rtlil::Cell>,
2022-01-05 01:08:25 +00:00
}
struct Context {
2022-01-05 01:09:08 +00:00
callables: BTreeMap<String, Callable>,
}
2022-01-04 22:05:25 +00:00
fn lower_process_statement(
ctx: &Context,
module: &mut rtlil::Module,
updates: &mut Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
stmt: &parser::proc::ProcStatement,
) -> Result<rtlil::CaseRule, CompileError> {
let rule = match stmt {
parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
parser::proc::ProcStatement::Assign(assig) => {
// FIXME: actually store this
let next_gen_id = format!("${}$next", assig.lhs);
module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
let next_wire = rtlil::SigSpec::Wire(next_gen_id.clone());
updates.push((rtlil::SigSpec::Wire(assig.lhs.to_owned()), next_wire.clone()));
let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
rtlil::CaseRule {
assign: vec![(next_wire, next_expr_wire)],
switches: vec![]
}
},
parser::proc::ProcStatement::Match(match_block) => {
let match_sig = lower_expression(ctx, module, &match_block.expr)?;
let mut cases = vec![];
for arm in &match_block.arms {
let case = lower_process_statement(ctx, module, updates, &arm.1)?;
let compare_sig = lower_expression(ctx, module, &arm.0)?;
cases.push((compare_sig, case));
};
let switch_rule = rtlil::SwitchRule {
signal: match_sig,
cases,
};
rtlil::CaseRule {
assign: vec![],
switches: vec![switch_rule],
}
},
parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
};
Ok(rule)
}
2022-01-17 00:15:27 +00:00
fn lower_process(
ctx: &Context,
module: &mut rtlil::Module,
process: &parser::proc::ProcBlock
) -> Result<(), CompileError> {
let mut updates = vec![];
let mut cases = vec![];
for stmt in &process.items {
let case = lower_process_statement(ctx, module, &mut updates, &stmt)?;
cases.push(case);
}
2022-01-17 00:15:27 +00:00
let sync_cond = rtlil::SyncCond::Posedge((*process.net.fragment()).into());
let sync_rule = rtlil::SyncRule {
cond: sync_cond,
assign: updates
2022-01-17 00:15:27 +00:00
};
if cases.len() != 1 {
panic!("only one expression per block, for now")
}
assert_eq!(cases.len(), 1);
2022-01-17 00:15:27 +00:00
let ir_proc = rtlil::Process {
id: module.make_genid("proc"),
root_case: cases.into_iter().next().unwrap(),
2022-01-17 00:15:27 +00:00
sync_rules: vec![sync_rule],
};
module.add_process(ir_proc);
Ok(())
}
2022-01-05 01:09:08 +00:00
fn lower_expression(
ctx: &Context,
module: &mut rtlil::Module,
expr: &parser::Expression,
) -> Result<rtlil::SigSpec, CompileError> {
2022-01-04 22:05:25 +00:00
match expr {
parser::Expression::Ident(ident) => Ok(rtlil::SigSpec::Wire(make_pubid(ident))),
2022-01-04 22:05:25 +00:00
parser::Expression::Call(call) => {
2022-01-05 01:09:08 +00:00
let args_resolved = call
.args
.iter()
.map(|expr| lower_expression(ctx, module, expr))
.collect::<Result<Vec<_>, _>>()?;
let callable = ctx
.callables
.get(call.name.fragment() as &str)
.ok_or_else(|| {
CompileError::new(CompileErrorKind::UndefinedReference(
call.name.fragment().to_string(),
))
})?;
2022-01-05 01:08:25 +00:00
2022-01-05 01:38:56 +00:00
if args_resolved.len() != callable.args.len() {
2022-01-14 14:32:00 +00:00
return Err(CompileError::new(CompileErrorKind::BadArgCount {
expected: callable.args.len(),
received: args_resolved.len(),
}));
2022-01-05 01:38:56 +00:00
}
2022-01-05 01:08:25 +00:00
let cell_id = module.make_genid(&callable.name);
let output_gen_id = format!("{}$out", &cell_id);
module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
2022-01-04 22:05:25 +00:00
module.add_cell(cell);
Ok(output_gen_wire)
2022-01-04 22:05:25 +00:00
}
2022-01-17 16:29:00 +00:00
// operations should really just desugar to callables
parser::Expression::Operation(_op) => todo!("operators not yet implemented"),
parser::Expression::Literal(lit) => {
Ok(rtlil::SigSpec::Const(*lit as i64, TODO_WIDTH))
},
2022-01-04 22:05:25 +00:00
}
}
2022-01-05 01:09:08 +00:00
fn lower_assignment(
ctx: &Context,
module: &mut rtlil::Module,
assignment: parser::Assign,
) -> Result<(), CompileError> {
let target_id = rtlil::SigSpec::Wire(make_pubid(assignment.lhs));
2022-01-05 01:08:25 +00:00
let return_wire = lower_expression(ctx, module, &assignment.expr)?;
2022-01-16 19:13:04 +00:00
module.add_connection(&target_id, &return_wire);
2022-01-04 22:05:25 +00:00
Ok(())
}
pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
let mut writer = rtlil::ILWriter::new();
2022-01-05 01:11:13 +00:00
let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name));
let context = Context {
2022-01-05 01:09:08 +00:00
callables: get_builtins()
.into_iter()
.map(|clb| (clb.name.to_owned(), clb))
.collect(),
};
2022-01-04 22:05:25 +00:00
writer.write_line("autoidx 1");
for (idx, port) in pa_module.ports.iter().enumerate() {
let dir_option = match port.direction {
parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
};
let wire = rtlil::Wire::new(
2022-01-05 01:11:13 +00:00
make_pubid(port.net.name),
2022-01-04 22:05:25 +00:00
port.net.width.unwrap_or(1) as u32,
2022-01-05 01:09:08 +00:00
Some(dir_option),
2022-01-04 22:05:25 +00:00
);
ir_module.add_wire(wire);
}
2022-01-16 20:46:44 +00:00
for item in pa_module.items {
match item {
parser::ModuleItem::Assign(assignment) => {
2022-01-05 01:09:08 +00:00
lower_assignment(&context, &mut ir_module, assignment)?
}
2022-01-17 00:15:27 +00:00
parser::ModuleItem::Proc(proc) => {
lower_process(&context, &mut ir_module, &proc)?
}
2022-01-04 22:05:25 +00:00
}
}
ir_module.write_rtlil(&mut writer);
Ok(writer.finish())
}