2022-01-05 01:08:25 +00:00
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use std::collections::BTreeMap;
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2022-01-05 01:09:08 +00:00
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use crate::builtin_cells::get_builtins;
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2022-01-04 22:05:25 +00:00
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use crate::parser;
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use crate::rtlil;
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2022-01-16 18:11:56 +00:00
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use crate::rtlil::RtlilWrite;
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2022-01-04 22:05:25 +00:00
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2022-01-17 14:37:07 +00:00
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/// lots of code is still not width-aware, this constant keeps track of that
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const TODO_WIDTH: u32 = 1;
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2022-01-04 22:05:25 +00:00
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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}
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#[derive(Debug)]
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2022-01-04 23:13:56 +00:00
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pub enum CompileErrorKind {
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2022-01-05 01:09:08 +00:00
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UndefinedReference(String),
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2022-01-14 14:32:00 +00:00
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BadArgCount { received: usize, expected: usize },
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2022-01-04 23:13:56 +00:00
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}
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#[derive(Debug)]
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pub struct CompileError {
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kind: CompileErrorKind,
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}
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impl CompileError {
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fn new(kind: CompileErrorKind) -> Self {
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2022-01-05 01:09:08 +00:00
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Self { kind }
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2022-01-04 23:13:56 +00:00
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}
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}
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pub enum GenericParam<T> {
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Unsolved,
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Solved(T),
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}
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pub enum Type {
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/// a wire of some width
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Wire(GenericParam<u32>),
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2022-01-04 23:13:56 +00:00
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}
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2022-01-05 01:08:25 +00:00
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impl Type {
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pub fn wire() -> Self {
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Self::Wire(GenericParam::Unsolved)
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}
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}
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pub struct CallArgument {
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pub name: String,
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pub atype: Type,
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}
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2022-01-04 23:13:56 +00:00
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// module that can be instantiated like a function
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pub struct Callable {
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2022-01-05 01:08:25 +00:00
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pub name: String,
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pub args: Vec<CallArgument>,
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pub ret: Type,
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2022-01-17 14:37:07 +00:00
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pub instantiate: Box<dyn Fn(&str, &[rtlil::SigSpec], &rtlil::SigSpec) -> rtlil::Cell>,
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2022-01-05 01:08:25 +00:00
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}
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struct Context {
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callables: BTreeMap<String, Callable>,
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2022-01-04 23:13:56 +00:00
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}
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2022-01-04 22:05:25 +00:00
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2022-01-17 14:37:07 +00:00
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fn lower_process_statement(
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ctx: &Context,
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module: &mut rtlil::Module,
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updates: &mut Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
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stmt: &parser::proc::ProcStatement,
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) -> Result<rtlil::CaseRule, CompileError> {
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let rule = match stmt {
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parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
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parser::proc::ProcStatement::Assign(assig) => {
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// FIXME: actually store this
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let next_gen_id = format!("${}$next", assig.lhs);
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
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let next_wire = rtlil::SigSpec::Wire(next_gen_id.clone());
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updates.push((rtlil::SigSpec::Wire(assig.lhs.to_owned()), next_wire.clone()));
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
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rtlil::CaseRule {
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assign: vec![(next_wire, next_expr_wire)],
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switches: vec![]
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}
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},
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parser::proc::ProcStatement::Match(match_block) => {
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let match_sig = lower_expression(ctx, module, &match_block.expr)?;
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let mut cases = vec![];
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for arm in &match_block.arms {
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let case = lower_process_statement(ctx, module, updates, &arm.1)?;
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let compare_sig = lower_expression(ctx, module, &arm.0)?;
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cases.push((compare_sig, case));
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};
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let switch_rule = rtlil::SwitchRule {
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signal: match_sig,
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cases,
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};
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rtlil::CaseRule {
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assign: vec![],
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switches: vec![switch_rule],
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}
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},
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parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
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};
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Ok(rule)
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}
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2022-01-17 00:15:27 +00:00
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fn lower_process(
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ctx: &Context,
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module: &mut rtlil::Module,
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process: &parser::proc::ProcBlock
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) -> Result<(), CompileError> {
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let mut updates = vec![];
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let mut cases = vec![];
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for stmt in &process.items {
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let case = lower_process_statement(ctx, module, &mut updates, &stmt)?;
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cases.push(case);
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}
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2022-01-17 00:15:27 +00:00
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let sync_cond = rtlil::SyncCond::Posedge((*process.net.fragment()).into());
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let sync_rule = rtlil::SyncRule {
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cond: sync_cond,
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assign: updates
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};
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if cases.len() != 1 {
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panic!("only one expression per block, for now")
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}
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assert_eq!(cases.len(), 1);
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2022-01-17 00:15:27 +00:00
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let ir_proc = rtlil::Process {
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id: module.make_genid("proc"),
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root_case: cases.into_iter().next().unwrap(),
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sync_rules: vec![sync_rule],
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};
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module.add_process(ir_proc);
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Ok(())
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}
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2022-01-05 01:09:08 +00:00
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fn lower_expression(
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ctx: &Context,
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module: &mut rtlil::Module,
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expr: &parser::Expression,
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) -> Result<rtlil::SigSpec, CompileError> {
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match expr {
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parser::Expression::Ident(ident) => Ok(rtlil::SigSpec::Wire(make_pubid(ident))),
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parser::Expression::Call(call) => {
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2022-01-05 01:09:08 +00:00
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let args_resolved = call
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.args
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.iter()
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.map(|expr| lower_expression(ctx, module, expr))
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.collect::<Result<Vec<_>, _>>()?;
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let callable = ctx
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.callables
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.get(call.name.fragment() as &str)
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.ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(
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call.name.fragment().to_string(),
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))
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})?;
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2022-01-05 01:08:25 +00:00
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2022-01-05 01:38:56 +00:00
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if args_resolved.len() != callable.args.len() {
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
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expected: callable.args.len(),
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received: args_resolved.len(),
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}));
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2022-01-05 01:38:56 +00:00
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}
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2022-01-05 01:08:25 +00:00
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let cell_id = module.make_genid(&callable.name);
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2022-01-17 14:37:07 +00:00
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let output_gen_id = format!("{}$out", &cell_id);
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module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
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let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
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let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
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module.add_cell(cell);
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Ok(output_gen_wire)
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}
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2022-01-17 16:29:00 +00:00
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// operations should really just desugar to callables
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2022-01-17 14:37:07 +00:00
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parser::Expression::Operation(_op) => todo!("operators not yet implemented"),
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parser::Expression::Literal(lit) => {
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Ok(rtlil::SigSpec::Const(*lit as i64, TODO_WIDTH))
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},
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}
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}
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2022-01-05 01:09:08 +00:00
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fn lower_assignment(
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ctx: &Context,
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module: &mut rtlil::Module,
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assignment: parser::Assign,
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) -> Result<(), CompileError> {
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2022-01-17 14:37:07 +00:00
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let target_id = rtlil::SigSpec::Wire(make_pubid(assignment.lhs));
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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2022-01-16 19:13:04 +00:00
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module.add_connection(&target_id, &return_wire);
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Ok(())
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}
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let mut writer = rtlil::ILWriter::new();
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2022-01-05 01:11:13 +00:00
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let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name));
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let context = Context {
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2022-01-05 01:09:08 +00:00
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callables: get_builtins()
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.into_iter()
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.map(|clb| (clb.name.to_owned(), clb))
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.collect(),
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};
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writer.write_line("autoidx 1");
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for (idx, port) in pa_module.ports.iter().enumerate() {
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let dir_option = match port.direction {
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parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
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parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
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};
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let wire = rtlil::Wire::new(
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make_pubid(port.net.name),
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port.net.width.unwrap_or(1) as u32,
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Some(dir_option),
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);
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ir_module.add_wire(wire);
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}
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2022-01-16 20:46:44 +00:00
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for item in pa_module.items {
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match item {
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parser::ModuleItem::Assign(assignment) => {
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2022-01-05 01:09:08 +00:00
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lower_assignment(&context, &mut ir_module, assignment)?
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}
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2022-01-17 00:15:27 +00:00
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parser::ModuleItem::Proc(proc) => {
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lower_process(&context, &mut ir_module, &proc)?
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}
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2022-01-04 22:05:25 +00:00
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}
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}
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ir_module.write_rtlil(&mut writer);
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Ok(writer.finish())
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}
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