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cargo fmt

main
NotAFile 2022-01-17 17:37:15 +01:00
parent 4d03535741
commit 43c27b97e9
7 changed files with 57 additions and 60 deletions
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10
src/builtin_cells.rs
View File

@ -58,12 +58,10 @@ fn make_binop_callable(name: &str, celltype: &'static str) -> Callable {
}
fn make_unnop_callable(name: &str, celltype: &'static str) -> Callable {
let args = vec![
CallArgument {
name: "A".to_owned(),
atype: Type::wire(),
},
];
let args = vec![CallArgument {
name: "A".to_owned(),
atype: Type::wire(),
}];
Callable {
name: name.to_owned(),
args,

29
src/frontend.rs
View File

@ -76,15 +76,18 @@ fn lower_process_statement(
module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
let next_wire = rtlil::SigSpec::Wire(next_gen_id.clone());
updates.push((rtlil::SigSpec::Wire(assig.lhs.to_owned()), next_wire.clone()));
updates.push((
rtlil::SigSpec::Wire(assig.lhs.to_owned()),
next_wire.clone(),
));
let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
rtlil::CaseRule {
assign: vec![(next_wire, next_expr_wire)],
switches: vec![]
switches: vec![],
}
},
}
parser::proc::ProcStatement::Match(match_block) => {
let match_sig = lower_expression(ctx, module, &match_block.expr)?;
let mut cases = vec![];
@ -92,7 +95,7 @@ fn lower_process_statement(
let case = lower_process_statement(ctx, module, updates, &arm.1)?;
let compare_sig = lower_expression(ctx, module, &arm.0)?;
cases.push((compare_sig, case));
};
}
let switch_rule = rtlil::SwitchRule {
signal: match_sig,
cases,
@ -101,7 +104,7 @@ fn lower_process_statement(
assign: vec![],
switches: vec![switch_rule],
}
},
}
parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
};
Ok(rule)
@ -110,7 +113,7 @@ fn lower_process_statement(
fn lower_process(
ctx: &Context,
module: &mut rtlil::Module,
process: &parser::proc::ProcBlock
process: &parser::proc::ProcBlock,
) -> Result<(), CompileError> {
let mut updates = vec![];
let mut cases = vec![];
@ -122,7 +125,7 @@ fn lower_process(
let sync_cond = rtlil::SyncCond::Posedge((*process.net.fragment()).into());
let sync_rule = rtlil::SyncRule {
cond: sync_cond,
assign: updates
assign: updates,
};
if cases.len() != 1 {
panic!("only one expression per block, for now")
@ -145,7 +148,6 @@ fn lower_expression(
match expr {
parser::Expression::Ident(ident) => Ok(rtlil::SigSpec::Wire(make_pubid(ident))),
parser::Expression::Call(call) => {
let args_resolved = call
.args
.iter()
@ -174,15 +176,14 @@ fn lower_expression(
module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
let cell =
(*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
module.add_cell(cell);
Ok(output_gen_wire)
}
// operations should really just desugar to callables
parser::Expression::Operation(_op) => todo!("operators not yet implemented"),
parser::Expression::Literal(lit) => {
Ok(rtlil::SigSpec::Const(*lit as i64, TODO_WIDTH))
},
parser::Expression::Literal(lit) => Ok(rtlil::SigSpec::Const(*lit as i64, TODO_WIDTH)),
}
}
@ -224,9 +225,7 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
parser::ModuleItem::Assign(assignment) => {
lower_assignment(&context, &mut ir_module, assignment)?
}
parser::ModuleItem::Proc(proc) => {
lower_process(&context, &mut ir_module, &proc)?
}
parser::ModuleItem::Proc(proc) => lower_process(&context, &mut ir_module, &proc)?,
}
}
ir_module.write_rtlil(&mut writer);

1
src/main.rs
View File

@ -4,7 +4,6 @@ mod literals;
mod parser;
mod rtlil;
use std::fs::File;
use std::io::prelude::*;
use std::path::PathBuf;

37
src/parser.rs
View File

@ -61,9 +61,18 @@ pub struct Assign<'a> {
#[derive(Debug)]
pub enum Operation<'a> {
And { a: Expression<'a>, b: Expression<'a> },
Or { a: Expression<'a>, b: Expression<'a> },
Xor { a: Expression<'a>, b: Expression<'a> },
And {
a: Expression<'a>,
b: Expression<'a>,
},
Or {
a: Expression<'a>,
b: Expression<'a>,
},
Xor {
a: Expression<'a>,
b: Expression<'a>,
},
Not(Expression<'a>),
}
@ -102,29 +111,17 @@ fn operation(input: Span) -> IResult<Span, Operation> {
alt((
map(
separated_pair(ws0(expression_nonrecurse), char('&'), ws0(expression)),
|(a, b)| Operation::And {
a,
b,
},
|(a, b)| Operation::And { a, b },
),
map(
separated_pair(ws0(expression_nonrecurse), char('|'), ws0(expression)),
|(a, b)| Operation::Or {
a,
b,
},
|(a, b)| Operation::Or { a, b },
),
map(
separated_pair(ws0(expression_nonrecurse), char('^'), ws0(expression)),
|(a, b)| Operation::Xor {
a,
b,
},
),
map(
preceded(char('~'), expression),
|expr| Operation::Not(expr),
|(a, b)| Operation::Xor { a, b },
),
map(preceded(char('~'), expression), |expr| Operation::Not(expr)),
))(input)
}
@ -148,7 +145,7 @@ fn call_item(input: Span) -> IResult<Span, Call> {
fn expression(input: Span) -> IResult<Span, Expression> {
alt((
map(ws0(operation), |op| Expression::Operation(Box::new(op))),
expression_nonrecurse
expression_nonrecurse,
))(input)
}

9
src/parser/module.rs
View File

@ -5,12 +5,13 @@ use nom::{
combinator::{consumed, map},
error::context,
multi::{many1, separated_list0},
sequence::{delimited, tuple, terminated},
sequence::{delimited, terminated, tuple},
};
use crate::parser::{
assign_statement, declaration, identifier, ws0, Assign, IResult,
NetDecl, Span, proc::{proc_block, ProcBlock},
assign_statement, declaration, identifier,
proc::{proc_block, ProcBlock},
ws0, Assign, IResult, NetDecl, Span,
};
#[derive(Debug)]
@ -119,5 +120,3 @@ mod test {
all_consuming(module_item)(" assign a = b ;".into()).unwrap();
}
}

23
src/parser/proc.rs
View File

@ -5,10 +5,12 @@ use nom::{
combinator::map,
error::context,
multi::{many1, separated_list0, separated_list1},
sequence::{delimited, tuple, separated_pair},
sequence::{delimited, separated_pair, tuple},
};
use crate::parser::{identifier, ws0, expression, Expression, IResult, Span, Assign, assign_statement};
use crate::parser::{
assign_statement, expression, identifier, ws0, Assign, Expression, IResult, Span,
};
#[derive(Debug)]
pub struct ProcBlock<'a> {
@ -45,18 +47,23 @@ fn match_block(input: Span) -> IResult<Span, MatchBlock> {
tuple((
ws0(tag("match")),
ws0(delimited(char('('), ws0(expression), char(')'))),
ws0(delimited(char('{'), separated_list1(char(','), ws0(match_arm)), char('}'))),
ws0(delimited(
char('{'),
separated_list1(char(','), ws0(match_arm)),
char('}'),
)),
)),
|(_, expr, arms)| MatchBlock {
expr,
arms
},
|(_, expr, arms)| MatchBlock { expr, arms },
),
)(input)
}
fn statement_block(input: Span) -> IResult<Span, Vec<ProcStatement>> {
delimited(char('{'), separated_list1(char(';'), ws0(proc_statement)), char('}'))(input)
delimited(
char('{'),
separated_list1(char(';'), ws0(proc_statement)),
char('}'),
)(input)
}
/// parse a statement that is valid inside a proc block

8
src/rtlil.rs
View File

@ -1,6 +1,6 @@
mod sync;
pub use sync::{Process, SyncCond, SyncRule, SwitchRule, CaseRule};
pub use sync::{CaseRule, Process, SwitchRule, SyncCond, SyncRule};
#[derive(Debug, Default)]
pub struct ILWriter {
@ -144,8 +144,7 @@ impl Module {
}
pub fn add_connection(&mut self, target: &SigSpec, source: &SigSpec) {
self.connections
.push((target.clone(), source.clone()))
self.connections.push((target.clone(), source.clone()))
}
pub fn add_cell(&mut self, cell: Cell) {
@ -201,8 +200,7 @@ impl Cell {
}
pub fn add_connection(&mut self, from: &str, to: &SigSpec) {
self.connections
.push((SigSpec::wire(from), to.clone()))
self.connections.push((SigSpec::wire(from), to.clone()))
}
}