notafile
/
futilehdl
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

clippy fix self

main
NotAFile 2022-01-14 15:34:57 +01:00
parent 266d3122c4
commit b9eb6222de
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/rtlil.rs
View File

@ -52,7 +52,7 @@ pub struct Wire {
impl Wire { impl Wire {
pub fn new(id: impl Into<String>, width: u32, port_info: Option<PortOption>) -> Self { pub fn new(id: impl Into<String>, width: u32, port_info: Option<PortOption>) -> Self {
Wire { Self {
id: id.into(), id: id.into(),
width, width,
port_info, port_info,
@ -90,7 +90,7 @@ pub struct Module {
impl Module { impl Module {
pub fn new(name: impl Into<String>) -> Self { pub fn new(name: impl Into<String>) -> Self {
Module { Self {
name: name.into(), name: name.into(),
wires: Default::default(), wires: Default::default(),
cells: Default::default(), cells: Default::default(),
@ -144,7 +144,7 @@ pub struct Cell {
impl Cell { impl Cell {
pub fn new(id: &str, celltype: &str) -> Self { pub fn new(id: &str, celltype: &str) -> Self {
Cell { Self {
id: id.into(), id: id.into(),
celltype: celltype.into(), celltype: celltype.into(),
parameters: Vec::new(), parameters: Vec::new(),