diff --git a/src/rtlil.rs b/src/rtlil.rs
index 6e02c9c..7146f5d 100644
--- a/src/rtlil.rs
+++ b/src/rtlil.rs
@@ -52,7 +52,7 @@ pub struct Wire {
 
 impl Wire {
     pub fn new(id: impl Into<String>, width: u32, port_info: Option<PortOption>) -> Self {
-        Wire {
+        Self {
             id: id.into(),
             width,
             port_info,
@@ -90,7 +90,7 @@ pub struct Module {
 
 impl Module {
     pub fn new(name: impl Into<String>) -> Self {
-        Module {
+        Self {
             name: name.into(),
             wires: Default::default(),
             cells: Default::default(),
@@ -144,7 +144,7 @@ pub struct Cell {
 
 impl Cell {
     pub fn new(id: &str, celltype: &str) -> Self {
-        Cell {
+        Self {
             id: id.into(),
             celltype: celltype.into(),
             parameters: Vec::new(),