cargo fmt

src/builtin_cells.rs

@@ -1,4 +1,4 @@
-use crate::frontend::{Callable, CallArgument, Type};
+use crate::frontend::{CallArgument, Callable, Type};
 use crate::rtlil;
 
 fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell {
@@ -12,8 +12,12 @@ fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell
 }
 
 fn instantiate_binop(celltype: &str, id: &str, args: &[String], ret: &str) -> rtlil::Cell {
-    let a = args.get(0).expect("wrong argcount slipped through type check");
+    let a = args
-    let b = args.get(1).expect("wrong argcount slipped through type check");
+        .get(0)
+        .expect("wrong argcount slipped through type check");
+    let b = args
+        .get(1)
+        .expect("wrong argcount slipped through type check");
 
     let mut cell = rtlil::Cell::new(id, celltype);
     cell.add_param("\\A_SIGNED", "0");
@@ -42,7 +46,7 @@ fn make_binop_callable(name: &str, celltype: &'static str) -> Callable {
         name: name.to_owned(),
         args,
         ret: Type::wire(),
-        instantiate: Box::new(move |id, args, ret| instantiate_binop(celltype, id, args, ret))
+        instantiate: Box::new(move |id, args, ret| instantiate_binop(celltype, id, args, ret)),
     }
 }
 

src/frontend.rs

@@ -1,8 +1,8 @@
 use std::collections::BTreeMap;
 
+use crate::builtin_cells::get_builtins;
 use crate::parser;
 use crate::rtlil;
-use crate::builtin_cells::get_builtins;
 
 fn make_pubid(id: &str) -> String {
     "\\".to_owned() + id
@@ -10,7 +10,7 @@ fn make_pubid(id: &str) -> String {
 
 #[derive(Debug)]
 pub enum CompileErrorKind {
-    UndefinedReference(String)
+    UndefinedReference(String),
 }
 
 #[derive(Debug)]
@@ -20,9 +20,7 @@ pub struct CompileError {
 
 impl CompileError {
     fn new(kind: CompileErrorKind) -> Self {
-        Self {
+        Self { kind }
-            kind
-        }
     }
 }
 
@@ -33,7 +31,7 @@ pub enum GenericParam<T> {
 
 pub enum Type {
     /// a wire of some width
-    Wire(GenericParam<u32>)
+    Wire(GenericParam<u32>),
 }
 
 impl Type {
@@ -52,26 +50,38 @@ pub struct Callable {
     pub name: String,
     pub args: Vec<CallArgument>,
     pub ret: Type,
-    pub instantiate: Box<dyn Fn(&str, &[String], &str) -> rtlil::Cell>
+    pub instantiate: Box<dyn Fn(&str, &[String], &str) -> rtlil::Cell>,
 }
 
 struct Context {
-    callables: BTreeMap<String, Callable>
+    callables: BTreeMap<String, Callable>,
 }
 
-fn lower_expression(ctx: &Context, module: &mut rtlil::Module, expr: &parser::Expression) -> Result<String, CompileError> {
+fn lower_expression(
+    ctx: &Context,
+    module: &mut rtlil::Module,
+    expr: &parser::Expression,
+) -> Result<String, CompileError> {
     match expr {
         parser::Expression::Ident(ident) => Ok(make_pubid(&ident)),
         parser::Expression::Call(call) => {
             let output_gen_id = module.make_genid("cell");
             module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None));
 
-            let args_resolved = call.args.iter()
+            let args_resolved = call
-                .map(|expr| lower_expression(ctx, module, expr)).collect::<Result<Vec<_>, _>>()?;
+                .args
+                .iter()
+                .map(|expr| lower_expression(ctx, module, expr))
+                .collect::<Result<Vec<_>, _>>()?;
 
-            let callable = ctx.callables.get(call.name.fragment() as &str).ok_or_else(|| {
+            let callable = ctx
-                CompileError::new(CompileErrorKind::UndefinedReference(call.name.fragment().to_string()))
+                .callables
-            })?;
+                .get(call.name.fragment() as &str)
+                .ok_or_else(|| {
+                    CompileError::new(CompileErrorKind::UndefinedReference(
+                        call.name.fragment().to_string(),
+                    ))
+                })?;
 
             let cell_id = module.make_genid(&callable.name);
 
@@ -83,7 +93,11 @@ fn lower_expression(ctx: &Context, module: &mut rtlil::Module, expr: &parser::Ex
     }
 }
 
-fn lower_assignment(ctx: &Context, module: &mut rtlil::Module, assignment: parser::Assign) -> Result<(), CompileError> {
+fn lower_assignment(
+    ctx: &Context,
+    module: &mut rtlil::Module,
+    assignment: parser::Assign,
+) -> Result<(), CompileError> {
     let target_id = make_pubid(&assignment.lhs);
     let return_wire = lower_expression(ctx, module, &assignment.expr)?;
     module.add_connection(target_id, return_wire);
@@ -93,7 +107,12 @@ fn lower_assignment(ctx: &Context, module: &mut rtlil::Module, assignment: parse
 pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
     let mut writer = rtlil::ILWriter::new();
     let mut ir_module = rtlil::Module::new(make_pubid(&pa_module.name));
-    let mut context = Context { callables: get_builtins().into_iter().map(|clb| (clb.name.to_owned(), clb)).collect() };
+    let mut context = Context {
+        callables: get_builtins()
+            .into_iter()
+            .map(|clb| (clb.name.to_owned(), clb))
+            .collect(),
+    };
     writer.write_line("autoidx 1");
     for (idx, port) in pa_module.ports.iter().enumerate() {
         let dir_option = match port.direction {
@@ -103,13 +122,15 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
         let wire = rtlil::Wire::new(
             make_pubid(&port.net.name),
             port.net.width.unwrap_or(1) as u32,
-            Some(dir_option)
+            Some(dir_option),
         );
         ir_module.add_wire(wire);
     }
     for stmt in pa_module.statements {
         match stmt {
-            parser::Statement::Assign(assignment) => lower_assignment(&context, &mut ir_module, assignment)?,
+            parser::Statement::Assign(assignment) => {
+                lower_assignment(&context, &mut ir_module, assignment)?
+            }
         }
     }
     ir_module.write_rtlil(&mut writer);

src/literals.rs

@@ -5,13 +5,12 @@ use nom::{
     combinator::{map_res, recognize},
     multi::{many0, many1},
     sequence::{preceded, terminated},
-    AsChar, FindToken, InputIter, InputLength, Offset, Slice
+    AsChar, FindToken, InputIter, InputLength, Offset, Slice,
 };
 
 use crate::parser::{IResult, Span};
 
-pub fn hexadecimal(input: Span) -> IResult<Span, u64>
+pub fn hexadecimal(input: Span) -> IResult<Span, u64> {
-{
     map_res(
         preceded(
             char('h'),

src/main.rs

@@ -1,8 +1,8 @@
+mod builtin_cells;
+mod frontend;
 mod literals;
 mod parser;
 mod rtlil;
-mod frontend;
-mod builtin_cells;
 
 use nom::error::convert_error;
 use std::fs::File;

src/parser.rs

@@ -166,10 +166,7 @@ fn call_item(input: Span) -> IResult<Span, Call> {
                 char(')'),
             ),
         )),
-        |(name, args)| Call {
+        |(name, args)| Call { name: name, args },
-            name: name,
-            args,
-        },
     )(input)
 }
 

src/rtlil.rs

@@ -47,7 +47,7 @@ pub struct Wire {
     /// width in bits
     width: u32,
     /// Port info if this is a port
-    port_info: Option<PortOption>
+    port_info: Option<PortOption>,
 }
 
 impl Wire {
@@ -55,7 +55,7 @@ impl Wire {
         Wire {
             id: id.into(),
             width,
-            port_info
+            port_info,
         }
     }