From 6cc7b3bceee1090bf10933c064924e08069ccb7c Mon Sep 17 00:00:00 2001 From: NotAFile Date: Wed, 5 Jan 2022 02:09:08 +0100 Subject: [PATCH] cargo fmt --- src/builtin_cells.rs | 12 ++++++---- src/frontend.rs | 57 ++++++++++++++++++++++++++++++-------------- src/literals.rs | 5 ++-- src/main.rs | 4 ++-- src/parser.rs | 5 +--- src/rtlil.rs | 4 ++-- 6 files changed, 54 insertions(+), 33 deletions(-) diff --git a/src/builtin_cells.rs b/src/builtin_cells.rs index 037cdc7..289b662 100644 --- a/src/builtin_cells.rs +++ b/src/builtin_cells.rs @@ -1,4 +1,4 @@ -use crate::frontend::{Callable, CallArgument, Type}; +use crate::frontend::{CallArgument, Callable, Type}; use crate::rtlil; fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell { @@ -12,8 +12,12 @@ fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell } fn instantiate_binop(celltype: &str, id: &str, args: &[String], ret: &str) -> rtlil::Cell { - let a = args.get(0).expect("wrong argcount slipped through type check"); - let b = args.get(1).expect("wrong argcount slipped through type check"); + let a = args + .get(0) + .expect("wrong argcount slipped through type check"); + let b = args + .get(1) + .expect("wrong argcount slipped through type check"); let mut cell = rtlil::Cell::new(id, celltype); cell.add_param("\\A_SIGNED", "0"); @@ -42,7 +46,7 @@ fn make_binop_callable(name: &str, celltype: &'static str) -> Callable { name: name.to_owned(), args, ret: Type::wire(), - instantiate: Box::new(move |id, args, ret| instantiate_binop(celltype, id, args, ret)) + instantiate: Box::new(move |id, args, ret| instantiate_binop(celltype, id, args, ret)), } } diff --git a/src/frontend.rs b/src/frontend.rs index 46fc152..d53c355 100644 --- a/src/frontend.rs +++ b/src/frontend.rs @@ -1,8 +1,8 @@ use std::collections::BTreeMap; +use crate::builtin_cells::get_builtins; use crate::parser; use crate::rtlil; -use crate::builtin_cells::get_builtins; fn make_pubid(id: &str) -> String { "\\".to_owned() + id @@ -10,7 +10,7 @@ fn make_pubid(id: &str) -> String { #[derive(Debug)] pub enum CompileErrorKind { - UndefinedReference(String) + UndefinedReference(String), } #[derive(Debug)] @@ -20,9 +20,7 @@ pub struct CompileError { impl CompileError { fn new(kind: CompileErrorKind) -> Self { - Self { - kind - } + Self { kind } } } @@ -33,7 +31,7 @@ pub enum GenericParam { pub enum Type { /// a wire of some width - Wire(GenericParam) + Wire(GenericParam), } impl Type { @@ -52,26 +50,38 @@ pub struct Callable { pub name: String, pub args: Vec, pub ret: Type, - pub instantiate: Box rtlil::Cell> + pub instantiate: Box rtlil::Cell>, } struct Context { - callables: BTreeMap + callables: BTreeMap, } -fn lower_expression(ctx: &Context, module: &mut rtlil::Module, expr: &parser::Expression) -> Result { +fn lower_expression( + ctx: &Context, + module: &mut rtlil::Module, + expr: &parser::Expression, +) -> Result { match expr { parser::Expression::Ident(ident) => Ok(make_pubid(&ident)), parser::Expression::Call(call) => { let output_gen_id = module.make_genid("cell"); module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None)); - let args_resolved = call.args.iter() - .map(|expr| lower_expression(ctx, module, expr)).collect::, _>>()?; + let args_resolved = call + .args + .iter() + .map(|expr| lower_expression(ctx, module, expr)) + .collect::, _>>()?; - let callable = ctx.callables.get(call.name.fragment() as &str).ok_or_else(|| { - CompileError::new(CompileErrorKind::UndefinedReference(call.name.fragment().to_string())) - })?; + let callable = ctx + .callables + .get(call.name.fragment() as &str) + .ok_or_else(|| { + CompileError::new(CompileErrorKind::UndefinedReference( + call.name.fragment().to_string(), + )) + })?; let cell_id = module.make_genid(&callable.name); @@ -83,7 +93,11 @@ fn lower_expression(ctx: &Context, module: &mut rtlil::Module, expr: &parser::Ex } } -fn lower_assignment(ctx: &Context, module: &mut rtlil::Module, assignment: parser::Assign) -> Result<(), CompileError> { +fn lower_assignment( + ctx: &Context, + module: &mut rtlil::Module, + assignment: parser::Assign, +) -> Result<(), CompileError> { let target_id = make_pubid(&assignment.lhs); let return_wire = lower_expression(ctx, module, &assignment.expr)?; module.add_connection(target_id, return_wire); @@ -93,7 +107,12 @@ fn lower_assignment(ctx: &Context, module: &mut rtlil::Module, assignment: parse pub fn lower_module(pa_module: parser::Module) -> Result { let mut writer = rtlil::ILWriter::new(); let mut ir_module = rtlil::Module::new(make_pubid(&pa_module.name)); - let mut context = Context { callables: get_builtins().into_iter().map(|clb| (clb.name.to_owned(), clb)).collect() }; + let mut context = Context { + callables: get_builtins() + .into_iter() + .map(|clb| (clb.name.to_owned(), clb)) + .collect(), + }; writer.write_line("autoidx 1"); for (idx, port) in pa_module.ports.iter().enumerate() { let dir_option = match port.direction { @@ -103,13 +122,15 @@ pub fn lower_module(pa_module: parser::Module) -> Result { let wire = rtlil::Wire::new( make_pubid(&port.net.name), port.net.width.unwrap_or(1) as u32, - Some(dir_option) + Some(dir_option), ); ir_module.add_wire(wire); } for stmt in pa_module.statements { match stmt { - parser::Statement::Assign(assignment) => lower_assignment(&context, &mut ir_module, assignment)?, + parser::Statement::Assign(assignment) => { + lower_assignment(&context, &mut ir_module, assignment)? + } } } ir_module.write_rtlil(&mut writer); diff --git a/src/literals.rs b/src/literals.rs index bfa6967..349d9aa 100644 --- a/src/literals.rs +++ b/src/literals.rs @@ -5,13 +5,12 @@ use nom::{ combinator::{map_res, recognize}, multi::{many0, many1}, sequence::{preceded, terminated}, - AsChar, FindToken, InputIter, InputLength, Offset, Slice + AsChar, FindToken, InputIter, InputLength, Offset, Slice, }; use crate::parser::{IResult, Span}; -pub fn hexadecimal(input: Span) -> IResult -{ +pub fn hexadecimal(input: Span) -> IResult { map_res( preceded( char('h'), diff --git a/src/main.rs b/src/main.rs index 43512f8..972db41 100644 --- a/src/main.rs +++ b/src/main.rs @@ -1,8 +1,8 @@ +mod builtin_cells; +mod frontend; mod literals; mod parser; mod rtlil; -mod frontend; -mod builtin_cells; use nom::error::convert_error; use std::fs::File; diff --git a/src/parser.rs b/src/parser.rs index 7f46583..a2bdeea 100644 --- a/src/parser.rs +++ b/src/parser.rs @@ -166,10 +166,7 @@ fn call_item(input: Span) -> IResult { char(')'), ), )), - |(name, args)| Call { - name: name, - args, - }, + |(name, args)| Call { name: name, args }, )(input) } diff --git a/src/rtlil.rs b/src/rtlil.rs index 64dbdbc..6e02c9c 100644 --- a/src/rtlil.rs +++ b/src/rtlil.rs @@ -47,7 +47,7 @@ pub struct Wire { /// width in bits width: u32, /// Port info if this is a port - port_info: Option + port_info: Option, } impl Wire { @@ -55,7 +55,7 @@ impl Wire { Wire { id: id.into(), width, - port_info + port_info, } }