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6317987ed6
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120a3c59f4
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@ -86,7 +86,7 @@ struct Context {
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/// map callable name to callable
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callables: BTreeMap<String, Callable>,
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/// map signal name to Signal
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signals: BTreeMap<String, Signal>,
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signals: BTreeMap<String, Signal>
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}
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impl Context {
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@ -95,9 +95,8 @@ impl Context {
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}
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fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
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self.get_signal(signame).ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned()))
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})
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self.get_signal(signame)
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.ok_or(CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned())))
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}
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}
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@ -114,23 +113,25 @@ fn lower_process_statement(
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let next_sig;
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if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
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next_sig = sig.clone();
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} else {
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}
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else {
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let next_gen_id = format!("${}$next", assig.lhs);
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
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next_sig = rtlil::SigSpec::Wire(next_gen_id);
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pctx.next_sigs
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.insert(assig.lhs.to_owned(), next_sig.clone());
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pctx.next_sigs.insert(assig.lhs.to_owned(), next_sig.clone());
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// trigger the modified value to update
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pctx.updates
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.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
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pctx.updates.push((
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ctx.try_get_signal(assig.lhs)?.sigspec(),
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next_sig.clone(),
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));
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};
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
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rtlil::CaseRule {
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assign: vec![(next_sig, next_expr_wire)],
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assign: vec![(next_sig.clone(), next_expr_wire)],
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switches: vec![],
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}
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}
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@ -197,15 +198,15 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
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let b = desugar_expression(b);
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parser::Call {
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name: "and".into(),
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args: vec![a, b],
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args: vec![a, b]
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}
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}
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},
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parser::Operation::Or { a, b } => {
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let a = desugar_expression(a);
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let b = desugar_expression(b);
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parser::Call {
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name: "or".into(),
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args: vec![a, b],
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args: vec![a, b]
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}
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}
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parser::Operation::Xor { a, b } => {
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@ -213,14 +214,14 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
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let b = desugar_expression(b);
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parser::Call {
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name: "xor".into(),
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args: vec![a, b],
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args: vec![a, b]
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}
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}
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parser::Operation::Not(a) => {
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let a = desugar_expression(a);
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parser::Call {
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name: "not".into(),
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args: vec![a],
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args: vec![a]
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}
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}
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}
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@ -232,13 +233,13 @@ fn desugar_expression<'a>(expr: parser::Expression<'a>) -> parser::Expression<'a
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parser::Expression::Ident(_) => expr,
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parser::Expression::Literal(_) => expr,
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parser::Expression::Call(mut call) => {
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let new_args = call.args.into_iter().map(desugar_expression).collect();
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let new_args = call.args.into_iter().map(|argex| desugar_expression(argex)).collect();
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call.args = new_args;
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parser::Expression::Call(call)
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}
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},
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parser::Expression::Operation(op) => {
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parser::Expression::Call(Box::new(desugar_operation(*op)))
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}
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},
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}
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}
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@ -252,7 +253,7 @@ fn lower_expression(
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parser::Expression::Ident(ident) => {
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let signal = ctx.try_get_signal(ident)?;
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Ok(signal.sigspec())
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}
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},
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parser::Expression::Call(call) => {
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let args_resolved = call
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.args
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@ -320,12 +321,9 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let sig = Signal {
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name: port.net.name.to_owned(),
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il_id: make_pubid(port.net.name),
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typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32)),
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typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32))
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};
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let sig = context
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.signals
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.entry(port.net.name.to_owned())
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.or_insert(sig);
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let sig = context.signals.entry(port.net.name.to_owned()).or_insert(sig);
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let dir_option = match port.direction {
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parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
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@ -47,11 +47,9 @@ fn main() {
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let lowered = crate::frontend::lower_module(res.1);
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match lowered {
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Ok(res) => {
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let mut file = File::create(opt.output.unwrap_or_else(|| "out.rtlil".into()))
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.expect("could not open file");
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file.write_all(res.as_bytes())
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.expect("failed to write output file");
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}
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let mut file = File::create(opt.output.unwrap_or("out.rtlil".into())).expect("could not open file");
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file.write_all(res.as_bytes()).expect("failed to write output file");
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},
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Err(err) => eprintln!("{:#?}", err),
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}
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}
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