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No commits in common. "6317987ed6ee8a555639ea76cabdbcb130e18222" and "120a3c59f41f25d25a85b1bcf56b574f6564bbc3" have entirely different histories.

2 changed files with 25 additions and 29 deletions

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@ -86,7 +86,7 @@ struct Context {
/// map callable name to callable /// map callable name to callable
callables: BTreeMap<String, Callable>, callables: BTreeMap<String, Callable>,
/// map signal name to Signal /// map signal name to Signal
signals: BTreeMap<String, Signal>, signals: BTreeMap<String, Signal>
} }
impl Context { impl Context {
@ -95,9 +95,8 @@ impl Context {
} }
fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> { fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
self.get_signal(signame).ok_or_else(|| { self.get_signal(signame)
CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned())) .ok_or(CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned())))
})
} }
} }
@ -114,23 +113,25 @@ fn lower_process_statement(
let next_sig; let next_sig;
if let Some(sig) = pctx.next_sigs.get(assig.lhs) { if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
next_sig = sig.clone(); next_sig = sig.clone();
} else { }
else {
let next_gen_id = format!("${}$next", assig.lhs); let next_gen_id = format!("${}$next", assig.lhs);
module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None)); module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
next_sig = rtlil::SigSpec::Wire(next_gen_id); next_sig = rtlil::SigSpec::Wire(next_gen_id);
pctx.next_sigs pctx.next_sigs.insert(assig.lhs.to_owned(), next_sig.clone());
.insert(assig.lhs.to_owned(), next_sig.clone());
// trigger the modified value to update // trigger the modified value to update
pctx.updates pctx.updates.push((
.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone())); ctx.try_get_signal(assig.lhs)?.sigspec(),
next_sig.clone(),
));
}; };
let next_expr_wire = lower_expression(ctx, module, &assig.expr)?; let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
rtlil::CaseRule { rtlil::CaseRule {
assign: vec![(next_sig, next_expr_wire)], assign: vec![(next_sig.clone(), next_expr_wire)],
switches: vec![], switches: vec![],
} }
} }
@ -197,15 +198,15 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
let b = desugar_expression(b); let b = desugar_expression(b);
parser::Call { parser::Call {
name: "and".into(), name: "and".into(),
args: vec![a, b], args: vec![a, b]
} }
} },
parser::Operation::Or { a, b } => { parser::Operation::Or { a, b } => {
let a = desugar_expression(a); let a = desugar_expression(a);
let b = desugar_expression(b); let b = desugar_expression(b);
parser::Call { parser::Call {
name: "or".into(), name: "or".into(),
args: vec![a, b], args: vec![a, b]
} }
} }
parser::Operation::Xor { a, b } => { parser::Operation::Xor { a, b } => {
@ -213,14 +214,14 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
let b = desugar_expression(b); let b = desugar_expression(b);
parser::Call { parser::Call {
name: "xor".into(), name: "xor".into(),
args: vec![a, b], args: vec![a, b]
} }
} }
parser::Operation::Not(a) => { parser::Operation::Not(a) => {
let a = desugar_expression(a); let a = desugar_expression(a);
parser::Call { parser::Call {
name: "not".into(), name: "not".into(),
args: vec![a], args: vec![a]
} }
} }
} }
@ -232,13 +233,13 @@ fn desugar_expression<'a>(expr: parser::Expression<'a>) -> parser::Expression<'a
parser::Expression::Ident(_) => expr, parser::Expression::Ident(_) => expr,
parser::Expression::Literal(_) => expr, parser::Expression::Literal(_) => expr,
parser::Expression::Call(mut call) => { parser::Expression::Call(mut call) => {
let new_args = call.args.into_iter().map(desugar_expression).collect(); let new_args = call.args.into_iter().map(|argex| desugar_expression(argex)).collect();
call.args = new_args; call.args = new_args;
parser::Expression::Call(call) parser::Expression::Call(call)
} },
parser::Expression::Operation(op) => { parser::Expression::Operation(op) => {
parser::Expression::Call(Box::new(desugar_operation(*op))) parser::Expression::Call(Box::new(desugar_operation(*op)))
} },
} }
} }
@ -252,7 +253,7 @@ fn lower_expression(
parser::Expression::Ident(ident) => { parser::Expression::Ident(ident) => {
let signal = ctx.try_get_signal(ident)?; let signal = ctx.try_get_signal(ident)?;
Ok(signal.sigspec()) Ok(signal.sigspec())
} },
parser::Expression::Call(call) => { parser::Expression::Call(call) => {
let args_resolved = call let args_resolved = call
.args .args
@ -320,12 +321,9 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
let sig = Signal { let sig = Signal {
name: port.net.name.to_owned(), name: port.net.name.to_owned(),
il_id: make_pubid(port.net.name), il_id: make_pubid(port.net.name),
typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32)), typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32))
}; };
let sig = context let sig = context.signals.entry(port.net.name.to_owned()).or_insert(sig);
.signals
.entry(port.net.name.to_owned())
.or_insert(sig);
let dir_option = match port.direction { let dir_option = match port.direction {
parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1), parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),

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@ -47,11 +47,9 @@ fn main() {
let lowered = crate::frontend::lower_module(res.1); let lowered = crate::frontend::lower_module(res.1);
match lowered { match lowered {
Ok(res) => { Ok(res) => {
let mut file = File::create(opt.output.unwrap_or_else(|| "out.rtlil".into())) let mut file = File::create(opt.output.unwrap_or("out.rtlil".into())).expect("could not open file");
.expect("could not open file"); file.write_all(res.as_bytes()).expect("failed to write output file");
file.write_all(res.as_bytes()) },
.expect("failed to write output file");
}
Err(err) => eprintln!("{:#?}", err), Err(err) => eprintln!("{:#?}", err),
} }
} }