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fixup rtlil identifiers

This commit is contained in:
NotAFile 2022-02-21 13:04:05 +01:00
parent 1de0846f96
commit f03c777e28
2 changed files with 25 additions and 37 deletions
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30
src/frontend/lowering.rs
View File

@ -12,11 +12,11 @@ fn lower_expression(
expr: &typed_ir::Expr,
) -> Result<rtlil::SigSpec, CompileError> {
let expr_width = ctx.types.get_width(expr.typ).expect("signal needs width");
let expr_wire_name = format!("$sig_{}", expr.id.0);
let expr_wire_name = format!("$_sig_{}", expr.id.0);
let expr_wire = rtlil::Wire::new(expr_wire_name.clone(), expr_width, None);
module.add_wire(expr_wire);
match &expr.kind {
ExprKind::Path(def) => Ok(rtlil::SigSpec::Wire(format!("$sig_{}", def.0))),
ExprKind::Path(def) => Ok(rtlil::SigSpec::Wire(format!("\\$sig_{}", def.0))),
ExprKind::Call {
called,
args,
@ -40,14 +40,8 @@ fn lower_expression(
cell.add_param("\\B_SIGNED", "0");
cell.add_param("\\B_WIDTH", &b_width.to_string());
cell.add_param("\\Y_WIDTH", &y_width.to_string());
cell.add_connection(
"\\A",
&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)),
);
cell.add_connection(
"\\B",
&rtlil::SigSpec::Wire(format!("$sig_{}", args[1].id.0)),
);
cell.add_connection("\\A", &args_resolved[0]);
cell.add_connection("\\B", &args_resolved[1]);
cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone()));
module.add_cell(cell);
} else if *called == ctx.callables.builtins.reduce_or {
@ -57,10 +51,7 @@ fn lower_expression(
cell.add_param("\\A_SIGNED", "0");
cell.add_param("\\A_WIDTH", &a_width.to_string());
cell.add_param("\\Y_WIDTH", &y_width.to_string());
cell.add_connection(
"\\A",
&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)),
);
cell.add_connection("\\A", &args_resolved[0]);
cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone()));
module.add_cell(cell);
} else if *called == ctx.callables.builtins.bitnot {
@ -70,10 +61,7 @@ fn lower_expression(
cell.add_param("\\A_SIGNED", "0");
cell.add_param("\\A_WIDTH", &a_width.to_string());
cell.add_param("\\Y_WIDTH", &y_width.to_string());
cell.add_connection(
"\\A",
&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)),
);
cell.add_connection("\\A", &args_resolved[0]);
cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone()));
module.add_cell(cell);
}
@ -93,7 +81,7 @@ fn lower_comb(
block: typed_ir::Block,
) -> Result<(), CompileError> {
for (num, sig) in block.signals.iter().enumerate() {
let sig_id = format!("$sig_{}", sig.id.0);
let sig_id = format!("\\$sig_{}", sig.id.0);
let port_width = ctx.types.get_width(sig.typ).expect("signal has no size");
module.add_wire(rtlil::Wire::new(
sig_id.clone(),
@ -102,13 +90,13 @@ fn lower_comb(
));
}
let ret_id = module.make_genid("ret");
let ret_id = make_pubid("ret");
module.add_wire(rtlil::Wire::new(
ret_id.clone(),
ctx.types
.get_width(block.expr.typ)
.expect("signal has no size"),
Some(rtlil::PortOption::Output(99)),
Some(rtlil::PortOption::Output(block.signals.len() as i32)),
));
let out_sig = lower_expression(ctx, module, &block.expr)?;
module.add_connection(&rtlil::SigSpec::Wire(ret_id), &out_sig);

12
src/main.rs
View File

@ -60,22 +60,23 @@ fn main() {
}
let mut frontendcontext = crate::frontend::Context::new();
let typed = frontendcontext.type_module(res.1);
if opt.debug {
println!("{:#?}", &typed);
let mut pretty_block = String::new();
if let Ok(block) = typed {
if opt.debug {
let mut pretty_block = String::new();
frontendcontext
.pretty_typed_block(&mut pretty_block, &block)
.unwrap();
println!("{}", &pretty_block);
}
let typed_inferred = frontendcontext.infer_types(block);
if opt.debug {
let mut pretty_block = String::new();
frontendcontext
.pretty_typed_block(&mut pretty_block, &typed_inferred)
.unwrap();
println!("{}", &pretty_block);
let lowered =
frontend::lowering::lower_block(&mut frontendcontext, typed_inferred);
}
let lowered = frontend::lowering::lower_block(&mut frontendcontext, typed_inferred);
match lowered {
Ok(res) => {
let mut file =
@ -90,4 +91,3 @@ fn main() {
}
}
}
}