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@ -1,255 +1,126 @@
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use std::collections::BTreeMap; |
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use super::types::{make_primitives, TypeStruct}; |
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use super::{make_pubid, CompileError, CompileErrorKind, Context, Signal, TODO_WIDTH}; |
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use crate::builtin_cells::get_builtins; |
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use crate::parser; |
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use crate::parser::expression::Expression; |
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use super::typed_ir; |
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use super::typed_ir::ExprKind; |
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use super::{make_pubid, CompileError, Context, TODO_WIDTH}; |
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use crate::rtlil; |
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use crate::rtlil::RtlilWrite; |
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/// context used when generating processes
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struct ProcContext { |
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updates: Vec<(rtlil::SigSpec, rtlil::SigSpec)>, |
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next_sigs: BTreeMap<String, rtlil::SigSpec>, |
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} |
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fn lower_process_statement( |
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ctx: &Context, |
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pctx: &mut ProcContext, |
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module: &mut rtlil::Module, |
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stmt: &parser::proc::ProcStatement, |
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) -> Result<rtlil::CaseRule, CompileError> { |
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let rule = match stmt { |
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parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"), |
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parser::proc::ProcStatement::Assign(assig) => { |
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// FIXME: actually store this
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let next_sig; |
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if let Some(sig) = pctx.next_sigs.get(assig.lhs) { |
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next_sig = sig.clone(); |
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} else { |
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let next_gen_id = format!("${}$next", assig.lhs); |
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None)); |
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next_sig = rtlil::SigSpec::Wire(next_gen_id); |
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pctx.next_sigs |
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.insert(assig.lhs.to_owned(), next_sig.clone()); |
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// trigger the modified value to update
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pctx.updates |
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.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone())); |
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}; |
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?; |
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rtlil::CaseRule { |
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assign: vec![(next_sig, next_expr_wire)], |
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switches: vec![], |
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} |
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} |
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parser::proc::ProcStatement::Match(match_block) => { |
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let match_sig = lower_expression(ctx, module, &match_block.expr)?; |
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let mut cases = vec![]; |
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for arm in &match_block.arms { |
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let case = lower_process_statement(ctx, pctx, module, &arm.1)?; |
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let compare_sig = lower_expression(ctx, module, &arm.0)?; |
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cases.push((compare_sig, case)); |
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} |
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let switch_rule = rtlil::SwitchRule { |
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signal: match_sig, |
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cases, |
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}; |
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rtlil::CaseRule { |
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assign: vec![], |
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switches: vec![switch_rule], |
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} |
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} |
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parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"), |
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}; |
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Ok(rule) |
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} |
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fn lower_process( |
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ctx: &Context, |
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module: &mut rtlil::Module, |
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process: &parser::proc::ProcBlock, |
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) -> Result<(), CompileError> { |
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let mut pctx = ProcContext { |
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updates: vec![], |
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next_sigs: BTreeMap::new(), |
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}; |
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let mut cases = vec![]; |
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for stmt in &process.items { |
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let case = lower_process_statement(ctx, &mut pctx, module, stmt)?; |
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cases.push(case); |
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} |
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let sync_sig = ctx.try_get_signal(process.net.fragment())?; |
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let sync_cond = rtlil::SyncCond::Posedge(sync_sig.sigspec()); |
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let sync_rule = rtlil::SyncRule { |
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cond: sync_cond, |
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assign: pctx.updates, |
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}; |
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if cases.len() != 1 { |
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panic!("only one expression per block, for now") |
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} |
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assert_eq!(cases.len(), 1); |
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let ir_proc = rtlil::Process { |
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id: module.make_genid("proc"), |
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root_case: cases.into_iter().next().unwrap(), |
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sync_rules: vec![sync_rule], |
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}; |
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module.add_process(ir_proc); |
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Ok(()) |
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} |
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fn desugar_binop<'a>(op: parser::expression::BinOp<'a>) -> parser::expression::Call<'a> { |
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let a = desugar_expression(op.a); |
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let b = desugar_expression(op.b); |
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let op_func = match op.kind { |
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parser::expression::BinOpKind::And => "and", |
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parser::expression::BinOpKind::Or => "or", |
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parser::expression::BinOpKind::Xor => "xor", |
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}; |
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parser::expression::Call { |
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name: op_func.into(), |
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args: vec![a, b], |
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} |
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} |
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fn desugar_unop<'a>(op: parser::expression::UnOp<'a>) -> parser::expression::Call<'a> { |
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let a = desugar_expression(op.a); |
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let op_func = match op.kind { |
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parser::expression::UnOpKind::BitNot => "not", |
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parser::expression::UnOpKind::Not => todo!("bin not"), |
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}; |
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parser::expression::Call { |
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name: op_func.into(), |
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args: vec![a], |
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} |
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} |
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fn desugar_expression<'a>(expr: Expression<'a>) -> Expression<'a> { |
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// TODO: allow ergonomic traversal of AST
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match expr { |
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Expression::Path(_) => expr, |
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Expression::Literal(_) => expr, |
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Expression::Call(mut call) => { |
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let new_args = call.args.into_iter().map(desugar_expression).collect(); |
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call.args = new_args; |
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Expression::Call(call) |
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} |
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Expression::BinOp(op) => Expression::Call(Box::new(desugar_binop(*op))), |
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Expression::UnOp(op) => Expression::Call(Box::new(desugar_unop(*op))), |
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} |
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} |
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fn lower_expression( |
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ctx: &Context, |
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module: &mut rtlil::Module, |
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expr: &Expression, |
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expr: &typed_ir::Expr, |
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) -> Result<rtlil::SigSpec, CompileError> { |
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let expr = desugar_expression(expr.clone()); |
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match expr { |
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Expression::Path(ident) => { |
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let signal = ctx.try_get_signal(ident)?; |
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Ok(signal.sigspec()) |
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} |
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Expression::Call(call) => { |
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let args_resolved = call |
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.args |
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let expr_width = ctx.types.get_width(expr.typ).expect("signal needs width"); |
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let expr_wire_name = format!("$sig_{}", expr.id.0); |
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let expr_wire = rtlil::Wire::new(expr_wire_name.clone(), expr_width, None); |
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module.add_wire(expr_wire); |
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match &expr.kind { |
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ExprKind::Path(def) => Ok(rtlil::SigSpec::Wire(format!("$sig_{}", def.0))), |
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ExprKind::Call { |
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called, |
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args, |
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genargs, |
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} => { |
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let args_resolved = args |
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.iter() |
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.map(|expr| lower_expression(ctx, module, expr)) |
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.collect::<Result<Vec<_>, _>>()?; |
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let callable = ctx |
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.callables |
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.get(call.name.fragment() as &str) |
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.ok_or_else(|| { |
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CompileError::new(CompileErrorKind::UndefinedReference( |
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call.name.fragment().to_string(), |
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)) |
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})?; |
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if args_resolved.len() != callable.argcount() { |
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return Err(CompileError::new(CompileErrorKind::BadArgCount { |
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expected: callable.argcount(), |
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received: args_resolved.len(), |
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})); |
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} |
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let callable = ctx.callables.get(*called); |
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let cell_id = module.make_genid(callable.name()); |
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let output_gen_id = format!("{}$out", &cell_id); |
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module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None)); |
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let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id); |
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// let cell =
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// (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
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// module.add_cell(cell);
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Ok(output_gen_wire) |
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if *called == ctx.callables.builtins.xor { |
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let a_width = ctx.types.get_width(args[0].typ).unwrap(); |
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let b_width = ctx.types.get_width(args[1].typ).unwrap(); |
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let y_width = ctx.types.get_width(expr.typ).unwrap(); |
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let mut cell = rtlil::Cell::new(&cell_id, "$xor"); |
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cell.add_param("\\A_SIGNED", "0"); |
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cell.add_param("\\A_WIDTH", &a_width.to_string()); |
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cell.add_param("\\B_SIGNED", "0"); |
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cell.add_param("\\B_WIDTH", &b_width.to_string()); |
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cell.add_param("\\Y_WIDTH", &y_width.to_string()); |
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cell.add_connection( |
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"\\A", |
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&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)), |
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); |
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cell.add_connection( |
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"\\B", |
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&rtlil::SigSpec::Wire(format!("$sig_{}", args[1].id.0)), |
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); |
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cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone())); |
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module.add_cell(cell); |
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} else if *called == ctx.callables.builtins.reduce_or { |
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let a_width = ctx.types.get_width(args[0].typ).unwrap(); |
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let y_width = ctx.types.get_width(expr.typ).unwrap(); |
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let mut cell = rtlil::Cell::new(&cell_id, "$reduce_or"); |
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cell.add_param("\\A_SIGNED", "0"); |
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cell.add_param("\\A_WIDTH", &a_width.to_string()); |
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cell.add_param("\\Y_WIDTH", &y_width.to_string()); |
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cell.add_connection( |
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"\\A", |
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&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)), |
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); |
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cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone())); |
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module.add_cell(cell); |
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} else if *called == ctx.callables.builtins.bitnot { |
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let a_width = ctx.types.get_width(args[0].typ).unwrap(); |
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let y_width = ctx.types.get_width(expr.typ).unwrap(); |
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let mut cell = rtlil::Cell::new(&cell_id, "$not"); |
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cell.add_param("\\A_SIGNED", "0"); |
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cell.add_param("\\A_WIDTH", &a_width.to_string()); |
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cell.add_param("\\Y_WIDTH", &y_width.to_string()); |
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cell.add_connection( |
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"\\A", |
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&rtlil::SigSpec::Wire(format!("$sig_{}", args[0].id.0)), |
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); |
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cell.add_connection("\\Y", &rtlil::SigSpec::Wire(expr_wire_name.clone())); |
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module.add_cell(cell); |
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} |
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// TODO: insert builtin cells here
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Ok(rtlil::SigSpec::Wire(expr_wire_name)) |
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} |
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// TODO: instantiate operators directly here instead of desugaring, once the callable infrastructure improves
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// to get better errors
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Expression::Literal(lit) => Ok(rtlil::SigSpec::Const( |
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lit.span().fragment().parse().unwrap(), |
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TODO_WIDTH, |
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ExprKind::Literal(lit) => Ok(rtlil::SigSpec::Const( |
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todo!(), |
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ctx.types.get_width(expr.typ).expect("signal has no size"), |
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)), |
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Expression::UnOp(_) => todo!("unary op"), |
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Expression::BinOp(_) => todo!("binary op"), |
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} |
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} |
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fn lower_assignment( |
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ctx: &Context, |
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module: &mut rtlil::Module, |
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assignment: parser::Assign, |
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) -> Result<(), CompileError> { |
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let target_id = ctx.try_get_signal(assignment.lhs)?.sigspec(); |
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let return_wire = lower_expression(ctx, module, &assignment.expr)?; |
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module.add_connection(&target_id, &return_wire); |
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Ok(()) |
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} |
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fn lower_comb( |
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ctx: &mut Context, |
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module: &mut rtlil::Module, |
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pa_comb: parser::comb::CombBlock, |
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block: typed_ir::Block, |
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) -> Result<(), CompileError> { |
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for (num, port) in pa_comb.ports.iter().enumerate() { |
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let port_id = make_pubid(port.net.name.fragment()); |
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let port_tyname = &port.net.typ; |
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ctx.try_get_type(port_tyname.name.fragment())?; |
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for (num, sig) in block.signals.iter().enumerate() { |
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let sig_id = format!("$sig_{}", sig.id.0); |
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let port_width = ctx.types.get_width(sig.typ).expect("signal has no size"); |
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module.add_wire(rtlil::Wire::new( |
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port_id.clone(), |
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TODO_WIDTH, |
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sig_id.clone(), |
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port_width, |
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Some(rtlil::PortOption::Input((num + 1) as i32)), |
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)); |
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let typ = TypeStruct::logic_width(TODO_WIDTH); |
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let signal = Signal { |
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name: port.net.name.fragment().to_string(), |
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il_id: port_id, |
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// TODO: CRIMES CRIMES CRIMES
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typ: Box::leak(Box::new(typ)), |
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}; |
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ctx.signals |
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.insert(port.net.name.fragment().to_string(), signal); |
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} |
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let ret_id = module.make_genid("ret"); |
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module.add_wire(rtlil::Wire::new( |
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ret_id.clone(), |
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TODO_WIDTH, |
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ctx.types |
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.get_width(block.expr.typ) |
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.expect("signal has no size"), |
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Some(rtlil::PortOption::Output(99)), |
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)); |
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let out_sig = lower_expression(ctx, module, &pa_comb.expr)?; |
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let out_sig = lower_expression(ctx, module, &block.expr)?; |
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module.add_connection(&rtlil::SigSpec::Wire(ret_id), &out_sig); |
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Ok(()) |
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} |
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> { |
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pub fn lower_block(context: &mut Context, block: typed_ir::Block) -> Result<String, CompileError> { |
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let mut writer = rtlil::ILWriter::new(); |
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let mut ir_module = rtlil::Module::new(make_pubid("test")); |
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lower_comb(context, &mut ir_module, block)?; |
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writer.write_line("autoidx 1"); |
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ir_module.write_rtlil(&mut writer); |
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Ok(writer.finish()) |
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NotAFile
6 months ago