start tracking signals

main
NotAFile 2022-01-17 21:02:11 +01:00
parent 057511f56c
commit e45f4ba142
1 changed files with 24 additions and 1 deletions

View File

@ -58,8 +58,23 @@ pub struct Callable {
pub instantiate: Box<dyn Fn(&str, &[rtlil::SigSpec], &rtlil::SigSpec) -> rtlil::Cell>, pub instantiate: Box<dyn Fn(&str, &[rtlil::SigSpec], &rtlil::SigSpec) -> rtlil::Cell>,
} }
/// A user-defined signal
pub struct Signal {
/// the user-visible name of the signal
pub name: String,
/// the id of the signal in RTLIL
pub il_id: Option<String>,
/// the type of the signal
pub typ: Type,
// unique ID of the signal
// pub uid: u64,
}
struct Context { struct Context {
/// map callable name to callable
callables: BTreeMap<String, Callable>, callables: BTreeMap<String, Callable>,
/// map signal name to Signal
signals: BTreeMap<String, Signal>
} }
fn lower_process_statement( fn lower_process_statement(
@ -255,11 +270,12 @@ fn lower_assignment(
pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> { pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
let mut writer = rtlil::ILWriter::new(); let mut writer = rtlil::ILWriter::new();
let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name)); let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name));
let context = Context { let mut context = Context {
callables: get_builtins() callables: get_builtins()
.into_iter() .into_iter()
.map(|clb| (clb.name.to_owned(), clb)) .map(|clb| (clb.name.to_owned(), clb))
.collect(), .collect(),
signals: BTreeMap::new(),
}; };
writer.write_line("autoidx 1"); writer.write_line("autoidx 1");
for (idx, port) in pa_module.ports.iter().enumerate() { for (idx, port) in pa_module.ports.iter().enumerate() {
@ -273,6 +289,13 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
Some(dir_option), Some(dir_option),
); );
ir_module.add_wire(wire); ir_module.add_wire(wire);
let sig = Signal {
name: port.net.name.to_owned(),
il_id: None,
typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32))
};
context.signals.insert(port.net.name.to_owned(), sig);
} }
for item in pa_module.items { for item in pa_module.items {
match item { match item {