add examples to docs

doc/examples/halfadd.fut

@@ -0,0 +1,10 @@
+module halfadd (
+	input wire a,
+	input wire b,
+	output wire sum,
+	output wire carry
+)
+{
+	assign sum = xor(a, b);
+	assign carry = and(a, b);
+}

doc/examples/identity.fut

@@ -0,0 +1,7 @@
+module identity (
+	input wire a,
+	output wire x
+	)
+{
+	assign x = a;
+}