refactor rtlir backend

main
notafile 2022-01-04 01:38:35 +01:00
parent 3f1546c323
commit 68306885d7
6 changed files with 386 additions and 31 deletions

210
Cargo.lock generated
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@ -2,13 +2,85 @@
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@ -32,8 +104,146 @@ dependencies = [
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@ -7,3 +7,4 @@ edition = "2021"
[dependencies]
nom = "7.1.0"
structopt = "0.3.25"

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@ -1,4 +1,10 @@
module top ( input wire x, output wire y )
module halfadd (
input wire a,
input wire b,
output wire sum,
output wire carry
)
{
assign x = y;
assign sum = xor(a, b);
assign carry = and(a, b);
}

View File

@ -3,6 +3,7 @@ mod parser;
mod rtlil;
use nom::error::{convert_error, VerboseError};
use structopt::StructOpt;
// custom IResult type for verboseerror
pub type IResult<I, O, E = VerboseError<I>> = nom::IResult<I, O, E>;

View File

@ -3,8 +3,7 @@ use nom::{
bytes::complete::tag,
character::complete::{alpha1, alphanumeric1, char, multispace0, multispace1},
combinator::{map, opt, recognize},
error::ParseError,
error::{context, convert_error, VerboseError},
error::{context, ParseError},
multi::{many0, many1, separated_list0},
sequence::{delimited, pair, preceded, separated_pair, terminated, tuple},
};
@ -58,7 +57,7 @@ pub struct PortDecl {
pub struct Module {
pub name: String,
pub ports: Vec<PortDecl>,
pub statements: Vec<Assign>,
pub statements: Vec<Statement>,
}
#[derive(Debug)]
@ -80,8 +79,8 @@ pub enum Operation {
#[derive(Debug)]
pub struct Call {
name: String,
params: Vec<Expression>,
pub name: String,
pub args: Vec<Expression>,
}
#[derive(Debug)]
@ -142,10 +141,17 @@ fn call_item(input: &str) -> IResult<&str, Call> {
map(
tuple((
ws0(identifier),
delimited(char('('), ws0(separated_list0(char(','), expression)), char(')'))
delimited(
char('('),
ws0(separated_list0(char(','), expression)),
char(')'),
),
)),
|(name, params)| Call { name: name.into(), params }
)(input)
|(name, args)| Call {
name: name.into(),
args,
},
)(input)
}
fn expression(input: &str) -> IResult<&str, Expression> {
@ -156,16 +162,18 @@ fn expression(input: &str) -> IResult<&str, Expression> {
))(input)
}
fn assign_statement(input: &str) -> IResult<&str, Assign> {
fn assign_statement(input: &str) -> IResult<&str, Statement> {
context(
"assignment",
delimited(
ws0(terminated(tag("assign"), multispace1)),
map(
separated_pair(ws0(identifier), char('='), ws0(expression)),
|(lhs, expr)| Assign {
lhs: lhs.into(),
expr: expr.into(),
|(lhs, expr)| {
Statement::Assign(Assign {
lhs: lhs.into(),
expr: expr.into(),
})
},
),
ws0(char(';')),
@ -228,5 +236,6 @@ mod test {
fn test_call() {
call_item("thing ( )").unwrap();
call_item("thing ( a , b , c )").unwrap();
call_item("thing(a,b,c)").unwrap();
}
}

View File

@ -37,18 +37,91 @@ impl ILWriter {
}
// the proper way
#[derive(Debug)]
pub enum WireOption {
Input(i32),
Output(i32),
}
#[derive(Debug)]
pub struct Wire {
id: String,
options: Vec<()>,
options: Vec<WireOption>,
}
struct Module {}
impl Wire {
fn new(id: impl Into<String>) -> Self {
Wire {
id: id.into(),
options: Default::default(),
}
}
fn write_rtlil(&self, writer: &mut ILWriter) {
let mut line = String::from("wire ");
for option in &self.options {
let option_str = match option {
WireOption::Input(num) => format!("input {} ", num),
WireOption::Output(num) => format!("output {} ", num),
};
line += &option_str;
}
line += &self.id;
writer.write_line(&line);
}
}
#[derive(Debug)]
struct Module {
name: String,
wires: Vec<Wire>,
cells: Vec<Cell>,
connections: Vec<(String, String)>,
gen_id: i32,
}
impl Module {
fn new(name: impl Into<String>) -> Self {
Module {
name: name.into(),
wires: Default::default(),
cells: Default::default(),
connections: Default::default(),
gen_id: 0,
}
}
fn add_wire(&mut self, wire: Wire) {
self.wires.push(wire)
}
fn write_rtlil(&self, writer: &mut ILWriter) {
writer.write_line(&format!("module {}", self.name));
writer.indent();
for wire in &self.wires {
wire.write_rtlil(writer);
}
for cell in &self.cells {
cell.write_rtlil(writer);
}
for conn in &self.connections {
writer.write_line(&format!("connect {} {}", conn.0, conn.1))
}
writer.dedent();
writer.write_line("end");
}
fn make_genid(&mut self, stem: &str) -> String {
let res = format!("${}${}", stem, self.gen_id);
self.gen_id += 1;
res
}
}
#[derive(Debug)]
struct Cell {
id: String,
celltype: String,
@ -88,6 +161,19 @@ impl Cell {
}
}
fn xor_cell(id: &str, a: &str, b: &str, y: &str) -> Cell {
let mut cell = Cell::new(id, "$xor");
cell.add_param("\\A_SIGNED", "0");
cell.add_param("\\A_WIDTH", "1");
cell.add_param("\\B_SIGNED", "0");
cell.add_param("\\B_WIDTH", "1");
cell.add_param("\\Y_WIDTH", "1");
cell.add_connection("\\A", a);
cell.add_connection("\\B", b);
cell.add_connection("\\Y", y);
cell
}
fn adder_cell(id: &str, a: &str, b: &str, y: &str) -> Cell {
let mut cell = Cell::new(id, "$and");
cell.add_param("\\A_SIGNED", "0");
@ -103,24 +189,66 @@ fn adder_cell(id: &str, a: &str, b: &str, y: &str) -> Cell {
// the hacky way
pub fn lower_module(module: parser::Module) -> String {
fn make_pubid(id: &str) -> String {
"\\".to_owned() + id
}
fn lower_expression(module: &mut Module, expr: &parser::Expression) -> String {
match expr {
parser::Expression::Ident(ident) => make_pubid(&ident),
parser::Expression::Call(call) => {
let output_gen_id = module.make_genid("cell");
module.add_wire(Wire::new(&output_gen_id));
let mut args_resolved = call.args.iter().map(|expr| lower_expression(module, expr));
let arg_a = args_resolved.next().unwrap();
let arg_b = args_resolved.next().unwrap();
let cell = match call.name.as_str() {
"and" => {
let cell_id = module.make_genid("and");
adder_cell(&cell_id, &arg_a, &arg_b, &output_gen_id)
},
"xor" => {
let cell_id = module.make_genid("xor");
xor_cell(&cell_id, &arg_a, &arg_b, &output_gen_id)
},
_ => todo!(),
};
module.cells.push(cell);
output_gen_id
}
parser::Expression::Operation(op) => todo!(),
}
}
fn lower_assignment(module: &mut Module, assignment: parser::Assign) {
let target_id = make_pubid(&assignment.lhs);
let return_wire = lower_expression(module, &assignment.expr);
module.connections.push((target_id, return_wire))
}
pub fn lower_module(pa_module: parser::Module) -> String {
let mut writer = ILWriter::new();
let mut ir_module = Module::new(format!("\\{}", pa_module.name));
writer.write_line("autoidx 1");
writer.write_line(&format!("module \\{}", module.name));
writer.indent();
for (num, port) in module.ports.iter().enumerate() {
writer.write_line(&format!(
"wire {} {} \\{}",
"output",
(num + 1),
port.net.name
))
for (idx, port) in pa_module.ports.iter().enumerate() {
let dir_option = match port.direction {
parser::PortDirection::Input => WireOption::Input(idx as i32 + 1),
parser::PortDirection::Output => WireOption::Output(idx as i32 + 1),
};
let wire = Wire {
id: make_pubid(&port.net.name),
options: vec![dir_option],
};
ir_module.wires.push(wire);
}
for stmt in module.statements {
// writer.write_line(&format!("connect \\{} \\{}", stmt.lhs, stmt.expr));
for stmt in pa_module.statements {
match stmt {
parser::Statement::Assign(assignment) => lower_assignment(&mut ir_module, assignment),
}
}
adder_cell("\\my_and", "\\a", "\\b", "\\y").write_rtlil(&mut writer);
writer.dedent();
writer.write_line("end");
ir_module.write_rtlil(&mut writer);
writer.finish()
}