move stuff, add rtlil, add operations
notafile
parent
93466defd0
commit
3f1546c323
138
src/main.rs
138
src/main.rs
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@ -1,144 +1,24 @@
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mod literals;
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mod parser;
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mod rtlil;
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use nom::{
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self,
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branch::alt,
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bytes::complete::tag,
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character::complete::{alpha1, alphanumeric1, char, multispace0},
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combinator::{map, opt, recognize},
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error::ParseError,
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error::{context, convert_error, VerboseError},
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multi::{many0, separated_list1},
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sequence::{delimited, pair, preceded, terminated, tuple},
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};
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use crate::literals::{decimal, hexadecimal};
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const REG_EXAMPLE: &'static str = "reg [0:15] msg = 16'hAAAA;";
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use nom::error::{convert_error, VerboseError};
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// custom IResult type for verboseerror
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pub type IResult<I, O, E = VerboseError<I>> = nom::IResult<I, O, E>;
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fn ws0<'a, F: 'a, O, E: ParseError<&'a str>>(
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inner: F,
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) -> impl FnMut(&'a str) -> IResult<&'a str, O, E>
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where
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F: FnMut(&'a str) -> IResult<&'a str, O, E>,
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{
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delimited(multispace0, inner, multispace0)
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}
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fn identifier(input: &str) -> IResult<&str, &str> {
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recognize(pair(
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alt((alpha1, tag("_"))),
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many0(alt((alphanumeric1, tag("_")))),
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))(input)
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}
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fn widthspec(input: &str) -> IResult<&str, u64> {
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delimited(char('['), ws0(decimal), char(']'))(input)
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}
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fn intliteral(input: &str) -> IResult<&str, (u64, u64)> {
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tuple((terminated(decimal, char('\'')), alt((decimal, hexadecimal))))(input)
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}
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#[derive(Debug)]
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struct NetDecl {
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name: String,
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width: Option<u64>,
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value: Option<(u64, u64)>,
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}
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#[derive(Debug)]
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enum PortDirection {
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Input,
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Output,
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}
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#[derive(Debug)]
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struct PortDecl {
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direction: PortDirection,
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net: NetDecl,
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}
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#[derive(Debug)]
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struct Module {
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name: String,
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ports: Vec<PortDecl>,
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}
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fn declaration(i: &str) -> IResult<&str, NetDecl> {
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let (i, (_, width, ident, value)) = tuple((
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ws0(alt((tag("reg"), tag("wire")))),
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opt(ws0(widthspec)),
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identifier,
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opt(preceded(ws0(char('=')), intliteral)),
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))(i)?;
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Ok((
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i,
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NetDecl {
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name: ident.into(),
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width,
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value,
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},
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))
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}
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fn port_decl(i: &str) -> IResult<&str, PortDecl> {
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map(
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tuple((
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alt((
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map(tag("input"), |_| PortDirection::Input),
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map(tag("output"), |_| PortDirection::Output),
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)),
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declaration,
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)),
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|(direction, net)| PortDecl { direction, net },
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)(i)
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}
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fn ports_list(input: &str) -> IResult<&str, Vec<PortDecl>> {
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context(
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"port declaration",
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separated_list1(ws0(char(',')), ws0(port_decl)),
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)(input)
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}
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fn module(input: &str) -> IResult<&str, Module> {
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context(
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"module",
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map(
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tuple((
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tag("module"),
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ws0(identifier),
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ws0(delimited(char('('), ws0(ports_list), char(')'))),
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)),
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|(_, name, ports)| Module {
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name: name.into(),
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ports,
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},
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),
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)(input)
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}
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fn main() {
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let input = include_str!("../identity.fut");
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let parsed = module(input);
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let parsed = parser::module(input);
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match parsed {
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Err(nom::Err::Error(err) | nom::Err::Failure(err)) => {
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print!("{}", convert_error(input, err))
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}
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Err(_) => (),
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Ok(res) => println!("{:#?}", res),
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}
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}
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#[cfg(test)]
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mod test {
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use super::*;
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#[test]
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fn test_decl() {
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declaration("input reg abcd").unwrap();
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Ok(res) => {
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println!("{:#?}", res);
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let lowered = crate::rtlil::lower_module(res.1);
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println!("{}", lowered);
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}
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}
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}
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@ -0,0 +1,232 @@
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use nom::{
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branch::alt,
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bytes::complete::tag,
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character::complete::{alpha1, alphanumeric1, char, multispace0, multispace1},
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combinator::{map, opt, recognize},
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error::ParseError,
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error::{context, convert_error, VerboseError},
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multi::{many0, many1, separated_list0},
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sequence::{delimited, pair, preceded, separated_pair, terminated, tuple},
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};
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use crate::literals::{decimal, hexadecimal};
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use crate::IResult;
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fn ws0<'a, F: 'a, O, E: ParseError<&'a str>>(
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inner: F,
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) -> impl FnMut(&'a str) -> IResult<&'a str, O, E>
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where
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F: FnMut(&'a str) -> IResult<&'a str, O, E>,
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{
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delimited(multispace0, inner, multispace0)
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}
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fn identifier(input: &str) -> IResult<&str, &str> {
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recognize(pair(
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alt((alpha1, tag("_"))),
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many0(alt((alphanumeric1, tag("_")))),
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))(input)
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}
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fn widthspec(input: &str) -> IResult<&str, u64> {
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delimited(char('['), ws0(decimal), char(']'))(input)
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}
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fn intliteral(input: &str) -> IResult<&str, (u64, u64)> {
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tuple((terminated(decimal, char('\'')), alt((decimal, hexadecimal))))(input)
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}
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#[derive(Debug)]
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pub struct NetDecl {
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pub name: String,
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pub width: Option<u64>,
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pub value: Option<(u64, u64)>,
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}
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#[derive(Debug)]
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pub enum PortDirection {
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Input,
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Output,
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}
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#[derive(Debug)]
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pub struct PortDecl {
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pub direction: PortDirection,
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pub net: NetDecl,
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}
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#[derive(Debug)]
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pub struct Module {
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pub name: String,
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pub ports: Vec<PortDecl>,
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pub statements: Vec<Assign>,
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}
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#[derive(Debug)]
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pub enum Statement {
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Assign(Assign),
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}
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#[derive(Debug)]
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pub struct Assign {
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pub lhs: String,
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pub expr: Expression,
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}
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#[derive(Debug)]
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pub enum Operation {
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And { a: String, b: Expression },
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Or { a: String, b: Expression },
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}
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#[derive(Debug)]
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pub struct Call {
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name: String,
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params: Vec<Expression>,
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}
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#[derive(Debug)]
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pub enum Expression {
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Ident(String),
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Call(Box<Call>),
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Operation(Box<Operation>),
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}
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fn declaration(i: &str) -> IResult<&str, NetDecl> {
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map(
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tuple((
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ws0(alt((tag("reg"), tag("wire")))),
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opt(ws0(widthspec)),
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identifier,
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opt(preceded(ws0(char('=')), intliteral)),
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)),
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|(_, width, ident, value)| NetDecl {
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name: ident.into(),
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width,
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value,
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},
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)(i)
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}
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fn port_decl(i: &str) -> IResult<&str, PortDecl> {
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map(
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tuple((
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alt((
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map(tag("input"), |_| PortDirection::Input),
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map(tag("output"), |_| PortDirection::Output),
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)),
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declaration,
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)),
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|(direction, net)| PortDecl { direction, net },
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)(i)
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}
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fn ports_list(input: &str) -> IResult<&str, Vec<PortDecl>> {
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separated_list0(ws0(char(',')), ws0(port_decl))(input)
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}
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fn operation(input: &str) -> IResult<&str, Operation> {
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// temporarily given up on before I learn the shunting yard algorithm
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alt((
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map(
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separated_pair(ws0(identifier), char('&'), ws0(expression)),
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|(a, b)| Operation::And { a: a.into(), b },
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),
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map(
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separated_pair(ws0(identifier), char('|'), ws0(expression)),
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|(a, b)| Operation::Or { a: a.into(), b },
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),
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))(input)
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}
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fn call_item(input: &str) -> IResult<&str, Call> {
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map(
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tuple((
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ws0(identifier),
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delimited(char('('), ws0(separated_list0(char(','), expression)), char(')'))
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)),
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|(name, params)| Call { name: name.into(), params }
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)(input)
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}
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fn expression(input: &str) -> IResult<&str, Expression> {
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alt((
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map(ws0(operation), |op| Expression::Operation(Box::new(op))),
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map(ws0(call_item), |call| Expression::Call(Box::new(call))),
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map(ws0(identifier), |ident| Expression::Ident(ident.into())),
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))(input)
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}
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fn assign_statement(input: &str) -> IResult<&str, Assign> {
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context(
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"assignment",
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delimited(
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ws0(terminated(tag("assign"), multispace1)),
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map(
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separated_pair(ws0(identifier), char('='), ws0(expression)),
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|(lhs, expr)| Assign {
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lhs: lhs.into(),
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expr: expr.into(),
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},
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),
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ws0(char(';')),
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),
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)(input)
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}
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pub fn module(input: &str) -> IResult<&str, Module> {
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context(
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"module",
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map(
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tuple((
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tag("module"),
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ws0(identifier),
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ws0(delimited(char('('), ws0(ports_list), char(')'))),
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ws0(delimited(
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char('{'),
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many1(ws0(assign_statement)),
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char('}'),
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)),
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)),
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|(_, name, ports, statements)| Module {
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name: name.into(),
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ports,
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statements,
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},
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),
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)(input)
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}
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#[cfg(test)]
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mod test {
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use super::*;
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#[test]
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fn test_decl() {
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declaration("reg abcd").unwrap();
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}
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#[test]
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fn test_operation() {
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operation(" a | b ").unwrap();
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operation(" a & b ").unwrap();
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}
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#[test]
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fn test_expression() {
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expression(" a ").unwrap();
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expression(" a | b ").unwrap();
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expression(" a | b | c ").unwrap();
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}
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#[test]
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fn test_assignment() {
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assign_statement(" assign a = b ; ").unwrap();
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assign_statement(" assign a = b | c ; ").unwrap();
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}
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#[test]
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fn test_call() {
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call_item("thing ( )").unwrap();
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call_item("thing ( a , b , c )").unwrap();
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}
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}
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@ -0,0 +1,126 @@
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use crate::parser;
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use std::collections::HashMap;
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#[derive(Debug, Default)]
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pub struct ILWriter {
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data: String,
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indent: usize,
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}
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// this would be much nicer if indent gave you a new writer
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// which would indent things
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impl ILWriter {
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fn new() -> Self {
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Default::default()
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}
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fn write_line(&mut self, line: &str) {
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self.data += &"\t".repeat(self.indent);
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self.data += line;
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self.data += "\n";
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}
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fn indent(&mut self) {
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self.indent += 1
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}
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fn dedent(&mut self) {
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self.indent = self
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.indent
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.checked_sub(1)
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.expect("tried to dedent negative amount")
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}
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fn finish(self) -> String {
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self.data
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}
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}
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// the proper way
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pub enum WireOption {
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Input(i32),
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Output(i32),
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}
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pub struct Wire {
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id: String,
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options: Vec<()>,
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}
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struct Module {}
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struct Cell {
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id: String,
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celltype: String,
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parameters: Vec<(String, String)>,
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connections: Vec<(String, String)>,
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}
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impl Cell {
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fn new(id: &str, celltype: &str) -> Self {
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Cell {
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id: id.into(),
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celltype: celltype.into(),
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parameters: Vec::new(),
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connections: Vec::new(),
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}
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}
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fn add_param(&mut self, name: &str, value: &str) {
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self.parameters.push((name.into(), value.into()))
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}
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fn add_connection(&mut self, from: &str, to: &str) {
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self.connections.push((from.into(), to.into()))
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}
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fn write_rtlil(&self, writer: &mut ILWriter) {
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writer.write_line(&format!("cell {} {}", self.celltype, self.id));
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writer.indent();
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for param in &self.parameters {
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writer.write_line(&format!("parameter {} {}", param.0, param.1))
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}
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for conn in &self.connections {
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writer.write_line(&format!("connect {} {}", conn.0, conn.1))
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}
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writer.dedent();
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writer.write_line("end");
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}
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}
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fn adder_cell(id: &str, a: &str, b: &str, y: &str) -> Cell {
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let mut cell = Cell::new(id, "$and");
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\B_SIGNED", "0");
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cell.add_param("\\B_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\B", b);
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cell.add_connection("\\Y", y);
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cell
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}
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// the hacky way
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pub fn lower_module(module: parser::Module) -> String {
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let mut writer = ILWriter::new();
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writer.write_line("autoidx 1");
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writer.write_line(&format!("module \\{}", module.name));
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writer.indent();
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for (num, port) in module.ports.iter().enumerate() {
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writer.write_line(&format!(
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"wire {} {} \\{}",
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"output",
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(num + 1),
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port.net.name
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))
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}
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for stmt in module.statements {
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// writer.write_line(&format!("connect \\{} \\{}", stmt.lhs, stmt.expr));
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}
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adder_cell("\\my_and", "\\a", "\\b", "\\y").write_rtlil(&mut writer);
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writer.dedent();
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writer.write_line("end");
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writer.finish()
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}
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