futilehdl/lib/builtins/main.hyd



comb reduce_or<T> (
	a: T
	)
	-> Logic<1> {
	reduce_or(a)
}
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00

fix rtlil generation 2022-02-20 21:44:58 +00:00			`comb reduce_or<T> (`
			`a: T`
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00			`)`
			`-> Logic<1> {`
more typechecking af callables 2022-02-18 11:59:53 +00:00			`reduce_or(a)`
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00			`}`