13 lines
167 B
Plaintext
13 lines
167 B
Plaintext
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module clockdiv_2 (
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input wire clk,
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input wire rst,
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output wire out_clk
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) {
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proc (clk) {
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match (rst) {
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0 => out_clk = 0,
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1 => out_clk = ~out_clk,
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}
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}
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}
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