149 lines
4.1 KiB
Rust
149 lines
4.1 KiB
Rust
use std::collections::BTreeMap;
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use crate::builtin_cells::get_builtins;
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use crate::parser;
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use crate::rtlil;
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use crate::rtlil::RtlilWrite;
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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}
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#[derive(Debug)]
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pub enum CompileErrorKind {
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UndefinedReference(String),
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BadArgCount { received: usize, expected: usize },
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}
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#[derive(Debug)]
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pub struct CompileError {
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kind: CompileErrorKind,
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}
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impl CompileError {
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fn new(kind: CompileErrorKind) -> Self {
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Self { kind }
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}
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}
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pub enum GenericParam<T> {
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Unsolved,
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Solved(T),
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}
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pub enum Type {
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/// a wire of some width
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Wire(GenericParam<u32>),
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}
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impl Type {
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pub fn wire() -> Self {
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Self::Wire(GenericParam::Unsolved)
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}
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}
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pub struct CallArgument {
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pub name: String,
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pub atype: Type,
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}
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// module that can be instantiated like a function
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pub struct Callable {
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pub name: String,
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pub args: Vec<CallArgument>,
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pub ret: Type,
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pub instantiate: Box<dyn Fn(&str, &[String], &str) -> rtlil::Cell>,
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}
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struct Context {
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callables: BTreeMap<String, Callable>,
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}
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fn lower_expression(
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ctx: &Context,
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module: &mut rtlil::Module,
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expr: &parser::Expression,
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) -> Result<String, CompileError> {
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match expr {
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parser::Expression::Ident(ident) => Ok(make_pubid(ident)),
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parser::Expression::Call(call) => {
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let output_gen_id = module.make_genid("cell");
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module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None));
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let args_resolved = call
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.args
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.iter()
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.map(|expr| lower_expression(ctx, module, expr))
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.collect::<Result<Vec<_>, _>>()?;
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let callable = ctx
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.callables
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.get(call.name.fragment() as &str)
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.ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(
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call.name.fragment().to_string(),
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))
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})?;
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if args_resolved.len() != callable.args.len() {
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
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expected: callable.args.len(),
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received: args_resolved.len(),
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}));
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}
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let cell_id = module.make_genid(&callable.name);
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let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_id);
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module.add_cell(cell);
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Ok(output_gen_id)
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}
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parser::Expression::Operation(_op) => todo!(),
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}
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}
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fn lower_assignment(
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ctx: &Context,
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module: &mut rtlil::Module,
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assignment: parser::Assign,
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) -> Result<(), CompileError> {
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let target_id = make_pubid(assignment.lhs);
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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module.add_connection(&target_id, &return_wire);
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Ok(())
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}
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid(pa_module.name));
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let context = Context {
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callables: get_builtins()
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.into_iter()
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.map(|clb| (clb.name.to_owned(), clb))
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.collect(),
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};
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writer.write_line("autoidx 1");
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for (idx, port) in pa_module.ports.iter().enumerate() {
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let dir_option = match port.direction {
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parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
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parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
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};
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let wire = rtlil::Wire::new(
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make_pubid(port.net.name),
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port.net.width.unwrap_or(1) as u32,
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Some(dir_option),
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);
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ir_module.add_wire(wire);
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}
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for item in pa_module.items {
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match item {
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parser::ModuleItem::Assign(assignment) => {
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lower_assignment(&context, &mut ir_module, assignment)?
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}
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parser::ModuleItem::Proc(_proc) => todo!("lowering process"),
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}
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}
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ir_module.write_rtlil(&mut writer);
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Ok(writer.finish())
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}
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