From b71f9f09ae4a25a18be2eb9dde3591a6c3374b8d Mon Sep 17 00:00:00 2001
From: NotAFile <notafile@gmail.com>
Date: Tue, 5 Apr 2022 16:42:30 +0200
Subject: [PATCH] rename typed_ir::Block to Body

---
 src/frontend.rs            | 6 +++---
 src/frontend/lowering.rs   | 4 ++--
 src/frontend/pretty_ir.rs  | 2 +-
 src/frontend/type_infer.rs | 2 +-
 src/frontend/typed_ir.rs   | 2 +-
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/frontend.rs b/src/frontend.rs
index c0478ba..ff980d4 100644
--- a/src/frontend.rs
+++ b/src/frontend.rs
@@ -43,7 +43,7 @@ impl CompileError {
 
 #[derive(Debug)]
 pub struct Module {
-    pub blocks: Vec<typed_ir::Block>,
+    pub blocks: Vec<typed_ir::Body>,
 }
 
 pub struct Context {
@@ -276,7 +276,7 @@ impl Context {
     fn type_comb(
         &mut self,
         comb: &parser::comb::CombBlock,
-    ) -> Result<typed_ir::Block, CompileError> {
+    ) -> Result<typed_ir::Body, CompileError> {
         let mut signals = Vec::new();
 
         let callable_id = self.callable_from_block(comb)?;
@@ -296,7 +296,7 @@ impl Context {
 
         let root_expr = self.type_expression(&comb.expr)?;
 
-        Ok(typed_ir::Block {
+        Ok(typed_ir::Body {
             signature: callable_id,
             signals,
             expr: root_expr,
diff --git a/src/frontend/lowering.rs b/src/frontend/lowering.rs
index c8546f7..0058506 100644
--- a/src/frontend/lowering.rs
+++ b/src/frontend/lowering.rs
@@ -109,7 +109,7 @@ fn lower_expression(
 fn lower_comb(
     ctx: &mut Context,
     module: &mut rtlil::Module,
-    block: &typed_ir::Block,
+    block: &typed_ir::Body,
 ) -> Result<(), CompileError> {
     for (num, sig) in block.signals.iter().enumerate() {
         let sig_id = format!("\\$sig_{}", sig.id.0);
@@ -134,7 +134,7 @@ fn lower_comb(
     Ok(())
 }
 
-pub fn lower_block(context: &mut Context, block: &typed_ir::Block) -> Result<String, CompileError> {
+pub fn lower_block(context: &mut Context, block: &typed_ir::Body) -> Result<String, CompileError> {
     let mut writer = rtlil::ILWriter::new();
     let mut ir_module = rtlil::Module::new(make_pubid("test"));
 
diff --git a/src/frontend/pretty_ir.rs b/src/frontend/pretty_ir.rs
index dbd0af9..688a94c 100644
--- a/src/frontend/pretty_ir.rs
+++ b/src/frontend/pretty_ir.rs
@@ -5,7 +5,7 @@ impl Context {
     pub fn pretty_typed_block(
         &self,
         w: &mut dyn std::fmt::Write,
-        block: &typed_ir::Block,
+        block: &typed_ir::Body,
     ) -> std::fmt::Result {
         let callsig = self.callables.get(block.signature);
         {
diff --git a/src/frontend/type_infer.rs b/src/frontend/type_infer.rs
index c2999c3..45be49e 100644
--- a/src/frontend/type_infer.rs
+++ b/src/frontend/type_infer.rs
@@ -3,7 +3,7 @@ use super::types;
 use super::Context;
 
 impl Context {
-    pub fn infer_types(&mut self, mut block: typed_ir::Block) -> typed_ir::Block {
+    pub fn infer_types(&mut self, mut block: typed_ir::Body) -> typed_ir::Body {
         let new_root = self.infer_expr_types(&block.expr);
         block.expr = new_root;
         block
diff --git a/src/frontend/typed_ir.rs b/src/frontend/typed_ir.rs
index 95d0f51..07395f1 100644
--- a/src/frontend/typed_ir.rs
+++ b/src/frontend/typed_ir.rs
@@ -57,7 +57,7 @@ pub struct Signal {
 
 /// A block of HDL code, e.g. comb block
 #[derive(Debug, Clone)]
-pub struct Block {
+pub struct Body {
     pub signature: CallableId,
     pub signals: Vec<Signal>,
     pub expr: Expr,