make examples parse with new parser

doc/examples/clockdiv.fut

@@ -1,8 +1,8 @@
 module clockdiv_2 (
-	input wire clk,
-	input wire rst,
-	output wire out_clk
-) {
+	clk: Logic,
+	rst: Logic
+) -> Logic
+{
 	proc (clk) {
 		match (~rst) {
 			0 => out_clk = 0,

doc/examples/comparator.fut

@@ -1,7 +1,7 @@
 module comparator (
-	input wire [8] a,
-	input wire [8] b,
-	output wire eq
-) {
+	a: Logic<8>,
+	b: Logic<8>
+) -> Logic
+{
 	assign eq = ~reduce_or(a ^ b);
 }

doc/examples/halfadd.fut

@@ -1,9 +1,7 @@
 module halfadd (
-	input wire a,
-	input wire b,
-	output wire sum,
-	output wire carry
-)
+	a: Logic,
+	b: Logic
+) -> (Logic, Logic)
 {
 	assign sum = a ^ b;
 	assign carry = a & b;

doc/examples/identity.fut

@@ -1,7 +1,6 @@
 module identity (
-	input wire a,
-	output wire x
-	)
+	a: Logic
+	) -> Logic
 {
 	assign x = a;
 }