diff --git a/src/frontend/lowering.rs b/src/frontend/lowering.rs
index f3c188f..2ad8720 100644
--- a/src/frontend/lowering.rs
+++ b/src/frontend/lowering.rs
@@ -140,8 +140,8 @@ fn lower_comb(
             .expect("signal has no size"),
         Some(rtlil::PortOption::Output(block.signals.len() as i32)),
     ));
-    for (_, expr) in &block.exprs {
-        let expr_wire = lower_expression(ctx, module, block, &expr)?;
+    for expr in block.exprs.values() {
+        let expr_wire = lower_expression(ctx, module, block, expr)?;
         module.add_connection(&wire_for_expr(expr.id), &expr_wire);
     }
     let out_sig = wire_for_expr(block.expr);
diff --git a/src/frontend/pretty_ir.rs b/src/frontend/pretty_ir.rs
index 3c7f9bb..f88b698 100644
--- a/src/frontend/pretty_ir.rs
+++ b/src/frontend/pretty_ir.rs
@@ -41,8 +41,8 @@ impl Context {
             self.types.pretty_type(&mut typ_pretty, sig.typ)?;
             writeln!(w, "sig_{}: {}", sig.id.0, typ_pretty)?
         }
-        for (_, expr) in &body.exprs {
-            self.pretty_typed_expr(w, &expr)?;
+        for expr in body.exprs.values() {
+            self.pretty_typed_expr(w, expr)?;
         }
         writeln!(w, "return _{}", body.expr.0)?;
         Ok(())