move lowering code
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commit
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362
src/frontend.rs
362
src/frontend.rs
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@ -1,17 +1,22 @@
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use std::borrow::Borrow;
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use std::cell::Cell;
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use std::collections::BTreeMap;
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use crate::builtin_cells::get_builtins;
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use crate::parser;
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use crate::parser::expression::Expression;
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use super::parser;
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use crate::rtlil;
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use crate::rtlil::RtlilWrite;
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pub use callable::Callable;
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pub use types::{make_primitives, Type, TypeStruct};
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mod callable;
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#[cfg(never)]
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pub mod lowering;
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pub mod typed_ir;
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pub mod types;
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use crate::builtin_cells::get_builtins;
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// pub use lowering::lower_module;
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/// lots of code is still not width-aware, this constant keeps track of that
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const TODO_WIDTH: u32 = 1;
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@ -23,6 +28,7 @@ fn make_pubid(id: &str) -> String {
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pub enum CompileErrorKind {
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UndefinedReference(String),
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BadArgCount { received: usize, expected: usize },
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TodoError(String),
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}
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#[derive(Debug)]
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@ -54,291 +60,119 @@ impl<'ctx> Signal<'ctx> {
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}
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}
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/// context used when generating processes
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struct ProcContext {
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updates: Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
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next_sigs: BTreeMap<String, rtlil::SigSpec>,
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}
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struct Context<'ctx> {
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pub struct Context<'ctx> {
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/// map callable name to callable
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callables: BTreeMap<String, Callable<'ctx>>,
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/// types
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types: BTreeMap<String, TypeStruct<'ctx>>,
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/// map signal name to Signal
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signals: BTreeMap<String, Signal<'ctx>>,
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signals: BTreeMap<String, typed_ir::Signal<'ctx>>,
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/// incrementing counter for unique IDs
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ids: Counter,
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}
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struct Counter(Cell<usize>);
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impl Counter {
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fn new() -> Counter {
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Counter(Cell::new(0))
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}
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fn next(&self) -> usize {
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let next = self.0.get() + 1;
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self.0.set(next);
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next
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}
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}
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impl<'ctx> Context<'ctx> {
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fn get_signal(&self, signame: &str) -> Option<&Signal> {
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pub fn new() -> Self {
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Context {
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callables: get_builtins()
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.into_iter()
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.map(|clb| (clb.name().to_owned(), clb))
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.collect(),
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signals: BTreeMap::new(),
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types: make_primitives().into_iter().collect(),
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ids: Counter::new(),
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}
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}
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fn get_signal(&self, signame: &str) -> Option<&typed_ir::Signal> {
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self.signals.get(signame)
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}
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fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
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fn try_get_signal(&self, signame: &str) -> Result<&typed_ir::Signal, CompileError> {
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self.get_signal(signame).ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned()))
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})
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}
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fn try_get_type(&self, typename: &str) -> Result<Type, CompileError> {
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fn try_get_type(&'ctx self, typename: &str) -> Result<Type<'ctx>, CompileError> {
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self.types.get(typename).ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(typename.to_owned()))
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})
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}
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}
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fn lower_process_statement(
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ctx: &Context,
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pctx: &mut ProcContext,
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module: &mut rtlil::Module,
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stmt: &parser::proc::ProcStatement,
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) -> Result<rtlil::CaseRule, CompileError> {
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let rule = match stmt {
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parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
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parser::proc::ProcStatement::Assign(assig) => {
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// FIXME: actually store this
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let next_sig;
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if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
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next_sig = sig.clone();
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} else {
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let next_gen_id = format!("${}$next", assig.lhs);
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
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next_sig = rtlil::SigSpec::Wire(next_gen_id);
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pctx.next_sigs
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.insert(assig.lhs.to_owned(), next_sig.clone());
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// trigger the modified value to update
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pctx.updates
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.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
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};
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
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rtlil::CaseRule {
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assign: vec![(next_sig, next_expr_wire)],
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switches: vec![],
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}
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}
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parser::proc::ProcStatement::Match(match_block) => {
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let match_sig = lower_expression(ctx, module, &match_block.expr)?;
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let mut cases = vec![];
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for arm in &match_block.arms {
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let case = lower_process_statement(ctx, pctx, module, &arm.1)?;
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let compare_sig = lower_expression(ctx, module, &arm.0)?;
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cases.push((compare_sig, case));
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}
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let switch_rule = rtlil::SwitchRule {
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signal: match_sig,
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cases,
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};
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rtlil::CaseRule {
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assign: vec![],
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switches: vec![switch_rule],
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}
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}
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parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
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};
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Ok(rule)
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}
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fn lower_process(
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ctx: &Context,
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module: &mut rtlil::Module,
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process: &parser::proc::ProcBlock,
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) -> Result<(), CompileError> {
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let mut pctx = ProcContext {
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updates: vec![],
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next_sigs: BTreeMap::new(),
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};
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let mut cases = vec![];
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for stmt in &process.items {
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let case = lower_process_statement(ctx, &mut pctx, module, stmt)?;
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cases.push(case);
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}
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let sync_sig = ctx.try_get_signal(process.net.fragment())?;
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let sync_cond = rtlil::SyncCond::Posedge(sync_sig.sigspec());
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let sync_rule = rtlil::SyncRule {
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cond: sync_cond,
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assign: pctx.updates,
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};
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if cases.len() != 1 {
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panic!("only one expression per block, for now")
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}
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assert_eq!(cases.len(), 1);
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let ir_proc = rtlil::Process {
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id: module.make_genid("proc"),
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root_case: cases.into_iter().next().unwrap(),
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sync_rules: vec![sync_rule],
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};
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module.add_process(ir_proc);
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Ok(())
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}
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fn desugar_binop<'a>(op: parser::expression::BinOp<'a>) -> parser::expression::Call<'a> {
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let a = desugar_expression(op.a);
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let b = desugar_expression(op.b);
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let op_func = match op.kind {
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parser::expression::BinOpKind::And => "and",
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parser::expression::BinOpKind::Or => "or",
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parser::expression::BinOpKind::Xor => "xor",
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};
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parser::expression::Call {
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name: op_func.into(),
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args: vec![a, b],
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}
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}
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fn desugar_unop<'a>(op: parser::expression::UnOp<'a>) -> parser::expression::Call<'a> {
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let a = desugar_expression(op.a);
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let op_func = match op.kind {
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parser::expression::UnOpKind::BitNot => "not",
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parser::expression::UnOpKind::Not => todo!(),
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};
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parser::expression::Call {
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name: op_func.into(),
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args: vec![a],
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}
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}
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fn desugar_expression<'a>(expr: Expression<'a>) -> Expression<'a> {
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// TODO: allow ergonomic traversal of AST
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match expr {
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Expression::Path(_) => expr,
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Expression::Literal(_) => expr,
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Expression::Call(mut call) => {
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let new_args = call.args.into_iter().map(desugar_expression).collect();
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call.args = new_args;
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Expression::Call(call)
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}
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Expression::BinOp(op) => Expression::Call(Box::new(desugar_binop(*op))),
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Expression::UnOp(op) => Expression::Call(Box::new(desugar_unop(*op))),
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}
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}
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fn lower_expression(
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ctx: &Context,
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module: &mut rtlil::Module,
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expr: &Expression,
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) -> Result<rtlil::SigSpec, CompileError> {
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let expr = desugar_expression(expr.clone());
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match expr {
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Expression::Path(ident) => {
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let signal = ctx.try_get_signal(ident)?;
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Ok(signal.sigspec())
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}
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Expression::Call(call) => {
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let args_resolved = call
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.args
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.iter()
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.map(|expr| lower_expression(ctx, module, expr))
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.collect::<Result<Vec<_>, _>>()?;
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let callable = ctx
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.callables
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.get(call.name.fragment() as &str)
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.ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(
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call.name.fragment().to_string(),
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))
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})?;
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if args_resolved.len() != callable.argcount() {
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return Err(CompileError::new(CompileErrorKind::BadArgCount {
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expected: callable.argcount(),
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received: args_resolved.len(),
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}));
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}
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let cell_id = module.make_genid(callable.name());
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let output_gen_id = format!("{}$out", &cell_id);
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module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
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let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
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// let cell =
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// (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
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// module.add_cell(cell);
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Ok(output_gen_wire)
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}
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// TODO: instantiate operators directly here instead of desugaring, once the callable infrastructure improves
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// to get better errors
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Expression::Literal(lit) => Ok(rtlil::SigSpec::Const(
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lit.span().fragment().parse().unwrap(),
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TODO_WIDTH,
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)),
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Expression::UnOp(_) => todo!(),
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Expression::BinOp(_) => todo!(),
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}
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}
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fn lower_assignment(
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ctx: &Context,
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module: &mut rtlil::Module,
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assignment: parser::Assign,
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) -> Result<(), CompileError> {
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let target_id = ctx.try_get_signal(assignment.lhs)?.sigspec();
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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module.add_connection(&target_id, &return_wire);
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Ok(())
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}
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fn lower_comb(
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ctx: &mut Context,
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module: &mut rtlil::Module,
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pa_comb: parser::comb::CombBlock,
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) -> Result<(), CompileError> {
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for (num, port) in pa_comb.ports.iter().enumerate() {
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let port_id = make_pubid(port.net.name.fragment());
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let port_tyname = &port.net.typ;
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ctx.try_get_type(port_tyname.name.fragment())?;
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module.add_wire(rtlil::Wire::new(
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port_id.clone(),
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TODO_WIDTH,
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Some(rtlil::PortOption::Input((num + 1) as i32)),
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));
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let typ = TypeStruct::logic_width(TODO_WIDTH);
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let signal = Signal {
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name: port.net.name.fragment().to_string(),
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il_id: port_id,
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// TODO: CRIMES CRIMES CRIMES
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typ: Box::leak(Box::new(typ)),
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fn type_expression(
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&self,
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expr: &parser::expression::Expression,
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) -> Result<typed_ir::Expr, CompileError> {
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let typ = match expr {
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parser::expression::Expression::Path(name) => self.try_get_signal(name)?.typ,
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parser::expression::Expression::Literal(_) => todo!(),
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parser::expression::Expression::UnOp(op) => self.type_expression(&op.a)?.typ,
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parser::expression::Expression::BinOp(_) => todo!(),
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parser::expression::Expression::Call(call) => todo!(),
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};
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ctx.signals
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.insert(port.net.name.fragment().to_string(), signal);
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Ok(typed_ir::Expr {
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id: 0,
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inputs: vec![],
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typ: typ,
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})
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}
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let ret_id = module.make_genid("ret");
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module.add_wire(rtlil::Wire::new(
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ret_id.clone(),
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TODO_WIDTH,
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Some(rtlil::PortOption::Output(99)),
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));
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let out_sig = lower_expression(ctx, module, &pa_comb.expr)?;
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module.add_connection(&rtlil::SigSpec::Wire(ret_id), &out_sig);
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Ok(())
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}
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid("test"));
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let mut context = Context {
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callables: get_builtins()
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.into_iter()
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.map(|clb| (clb.name().to_owned(), clb))
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.collect(),
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signals: BTreeMap::new(),
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types: make_primitives().into_iter().collect(),
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};
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fn type_comb(
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&mut self,
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comb: &parser::comb::CombBlock,
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) -> Result<typed_ir::Block, CompileError> {
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let mut signals = Vec::new();
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writer.write_line("autoidx 1");
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for item in pa_module.items {
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match item {
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parser::ModuleItem::Comb(comb) => lower_comb(&mut context, &mut ir_module, comb)?,
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parser::ModuleItem::Proc(_) => todo!(),
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parser::ModuleItem::State(_) => todo!(),
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for port in comb.ports.iter() {
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let sig_id = self.ids.next();
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let sig_typename = &port.net.typ;
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let sig_type = self.try_get_type(sig_typename.name.fragment())?;
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let sig = typed_ir::Signal {
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id: sig_id as u32,
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typ: sig_type,
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};
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signals.push(sig);
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self.signals.insert(port.net.name.to_string(), sig);
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}
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let ret_typename = &comb.ret.name;
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let ret_type = self.try_get_type(&ret_typename.fragment())?;
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let root_expr = self.type_expression(&comb.expr)?;
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Ok(typed_ir::Block {
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signals,
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expr: root_expr,
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})
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}
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pub fn type_module(
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&'ctx mut self,
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module: parser::Module,
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) -> Result<typed_ir::Block<'ctx>, CompileError> {
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for item in module.items {
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let block = match &item {
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parser::ModuleItem::Comb(comb) => self.type_comb(comb)?,
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parser::ModuleItem::Proc(_) => todo!(),
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parser::ModuleItem::State(_) => todo!(),
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};
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return Ok(block);
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}
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Err(CompileError::new(CompileErrorKind::TodoError(
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"no blocks in module".to_string(),
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)))
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}
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ir_module.write_rtlil(&mut writer);
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Ok(writer.finish())
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}
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@ -0,0 +1,256 @@
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use std::collections::BTreeMap;
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use super::types::{make_primitives, TypeStruct};
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use super::{make_pubid, CompileError, CompileErrorKind, Context, Signal, TODO_WIDTH};
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use crate::builtin_cells::get_builtins;
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use crate::parser;
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use crate::parser::expression::Expression;
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use crate::rtlil;
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use crate::rtlil::RtlilWrite;
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|
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/// context used when generating processes
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struct ProcContext {
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updates: Vec<(rtlil::SigSpec, rtlil::SigSpec)>,
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next_sigs: BTreeMap<String, rtlil::SigSpec>,
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}
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fn lower_process_statement(
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ctx: &Context,
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pctx: &mut ProcContext,
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module: &mut rtlil::Module,
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stmt: &parser::proc::ProcStatement,
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) -> Result<rtlil::CaseRule, CompileError> {
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let rule = match stmt {
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parser::proc::ProcStatement::IfElse(_) => todo!("if/else unimplemented"),
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parser::proc::ProcStatement::Assign(assig) => {
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// FIXME: actually store this
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let next_sig;
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if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
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next_sig = sig.clone();
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} else {
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let next_gen_id = format!("${}$next", assig.lhs);
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module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
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next_sig = rtlil::SigSpec::Wire(next_gen_id);
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pctx.next_sigs
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.insert(assig.lhs.to_owned(), next_sig.clone());
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// trigger the modified value to update
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pctx.updates
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.push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
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};
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let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
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||||
rtlil::CaseRule {
|
||||
assign: vec![(next_sig, next_expr_wire)],
|
||||
switches: vec![],
|
||||
}
|
||||
}
|
||||
parser::proc::ProcStatement::Match(match_block) => {
|
||||
let match_sig = lower_expression(ctx, module, &match_block.expr)?;
|
||||
let mut cases = vec![];
|
||||
for arm in &match_block.arms {
|
||||
let case = lower_process_statement(ctx, pctx, module, &arm.1)?;
|
||||
let compare_sig = lower_expression(ctx, module, &arm.0)?;
|
||||
cases.push((compare_sig, case));
|
||||
}
|
||||
let switch_rule = rtlil::SwitchRule {
|
||||
signal: match_sig,
|
||||
cases,
|
||||
};
|
||||
rtlil::CaseRule {
|
||||
assign: vec![],
|
||||
switches: vec![switch_rule],
|
||||
}
|
||||
}
|
||||
parser::proc::ProcStatement::Block(_) => todo!("blocks unimplemented"),
|
||||
};
|
||||
Ok(rule)
|
||||
}
|
||||
|
||||
fn lower_process(
|
||||
ctx: &Context,
|
||||
module: &mut rtlil::Module,
|
||||
process: &parser::proc::ProcBlock,
|
||||
) -> Result<(), CompileError> {
|
||||
let mut pctx = ProcContext {
|
||||
updates: vec![],
|
||||
next_sigs: BTreeMap::new(),
|
||||
};
|
||||
let mut cases = vec![];
|
||||
for stmt in &process.items {
|
||||
let case = lower_process_statement(ctx, &mut pctx, module, stmt)?;
|
||||
cases.push(case);
|
||||
}
|
||||
|
||||
let sync_sig = ctx.try_get_signal(process.net.fragment())?;
|
||||
let sync_cond = rtlil::SyncCond::Posedge(sync_sig.sigspec());
|
||||
let sync_rule = rtlil::SyncRule {
|
||||
cond: sync_cond,
|
||||
assign: pctx.updates,
|
||||
};
|
||||
if cases.len() != 1 {
|
||||
panic!("only one expression per block, for now")
|
||||
}
|
||||
assert_eq!(cases.len(), 1);
|
||||
let ir_proc = rtlil::Process {
|
||||
id: module.make_genid("proc"),
|
||||
root_case: cases.into_iter().next().unwrap(),
|
||||
sync_rules: vec![sync_rule],
|
||||
};
|
||||
module.add_process(ir_proc);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn desugar_binop<'a>(op: parser::expression::BinOp<'a>) -> parser::expression::Call<'a> {
|
||||
let a = desugar_expression(op.a);
|
||||
let b = desugar_expression(op.b);
|
||||
let op_func = match op.kind {
|
||||
parser::expression::BinOpKind::And => "and",
|
||||
parser::expression::BinOpKind::Or => "or",
|
||||
parser::expression::BinOpKind::Xor => "xor",
|
||||
};
|
||||
parser::expression::Call {
|
||||
name: op_func.into(),
|
||||
args: vec![a, b],
|
||||
}
|
||||
}
|
||||
|
||||
fn desugar_unop<'a>(op: parser::expression::UnOp<'a>) -> parser::expression::Call<'a> {
|
||||
let a = desugar_expression(op.a);
|
||||
let op_func = match op.kind {
|
||||
parser::expression::UnOpKind::BitNot => "not",
|
||||
parser::expression::UnOpKind::Not => todo!(),
|
||||
};
|
||||
parser::expression::Call {
|
||||
name: op_func.into(),
|
||||
args: vec![a],
|
||||
}
|
||||
}
|
||||
|
||||
fn desugar_expression<'a>(expr: Expression<'a>) -> Expression<'a> {
|
||||
// TODO: allow ergonomic traversal of AST
|
||||
match expr {
|
||||
Expression::Path(_) => expr,
|
||||
Expression::Literal(_) => expr,
|
||||
Expression::Call(mut call) => {
|
||||
let new_args = call.args.into_iter().map(desugar_expression).collect();
|
||||
call.args = new_args;
|
||||
Expression::Call(call)
|
||||
}
|
||||
Expression::BinOp(op) => Expression::Call(Box::new(desugar_binop(*op))),
|
||||
Expression::UnOp(op) => Expression::Call(Box::new(desugar_unop(*op))),
|
||||
}
|
||||
}
|
||||
|
||||
fn lower_expression(
|
||||
ctx: &Context,
|
||||
module: &mut rtlil::Module,
|
||||
expr: &Expression,
|
||||
) -> Result<rtlil::SigSpec, CompileError> {
|
||||
let expr = desugar_expression(expr.clone());
|
||||
match expr {
|
||||
Expression::Path(ident) => {
|
||||
let signal = ctx.try_get_signal(ident)?;
|
||||
Ok(signal.sigspec())
|
||||
}
|
||||
Expression::Call(call) => {
|
||||
let args_resolved = call
|
||||
.args
|
||||
.iter()
|
||||
.map(|expr| lower_expression(ctx, module, expr))
|
||||
.collect::<Result<Vec<_>, _>>()?;
|
||||
|
||||
let callable = ctx
|
||||
.callables
|
||||
.get(call.name.fragment() as &str)
|
||||
.ok_or_else(|| {
|
||||
CompileError::new(CompileErrorKind::UndefinedReference(
|
||||
call.name.fragment().to_string(),
|
||||
))
|
||||
})?;
|
||||
|
||||
if args_resolved.len() != callable.argcount() {
|
||||
return Err(CompileError::new(CompileErrorKind::BadArgCount {
|
||||
expected: callable.argcount(),
|
||||
received: args_resolved.len(),
|
||||
}));
|
||||
}
|
||||
|
||||
let cell_id = module.make_genid(callable.name());
|
||||
|
||||
let output_gen_id = format!("{}$out", &cell_id);
|
||||
module.add_wire(rtlil::Wire::new(&output_gen_id, TODO_WIDTH, None));
|
||||
let output_gen_wire = rtlil::SigSpec::Wire(output_gen_id);
|
||||
|
||||
// let cell =
|
||||
// (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_wire);
|
||||
// module.add_cell(cell);
|
||||
Ok(output_gen_wire)
|
||||
}
|
||||
// TODO: instantiate operators directly here instead of desugaring, once the callable infrastructure improves
|
||||
// to get better errors
|
||||
Expression::Literal(lit) => Ok(rtlil::SigSpec::Const(
|
||||
lit.span().fragment().parse().unwrap(),
|
||||
TODO_WIDTH,
|
||||
)),
|
||||
Expression::UnOp(_) => todo!(),
|
||||
Expression::BinOp(_) => todo!(),
|
||||
}
|
||||
}
|
||||
|
||||
fn lower_assignment(
|
||||
ctx: &Context,
|
||||
module: &mut rtlil::Module,
|
||||
assignment: parser::Assign,
|
||||
) -> Result<(), CompileError> {
|
||||
let target_id = ctx.try_get_signal(assignment.lhs)?.sigspec();
|
||||
let return_wire = lower_expression(ctx, module, &assignment.expr)?;
|
||||
module.add_connection(&target_id, &return_wire);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn lower_comb(
|
||||
ctx: &mut Context,
|
||||
module: &mut rtlil::Module,
|
||||
pa_comb: parser::comb::CombBlock,
|
||||
) -> Result<(), CompileError> {
|
||||
for (num, port) in pa_comb.ports.iter().enumerate() {
|
||||
let port_id = make_pubid(port.net.name.fragment());
|
||||
let port_tyname = &port.net.typ;
|
||||
ctx.try_get_type(port_tyname.name.fragment())?;
|
||||
module.add_wire(rtlil::Wire::new(
|
||||
port_id.clone(),
|
||||
TODO_WIDTH,
|
||||
Some(rtlil::PortOption::Input((num + 1) as i32)),
|
||||
));
|
||||
let typ = TypeStruct::logic_width(TODO_WIDTH);
|
||||
let signal = Signal {
|
||||
name: port.net.name.fragment().to_string(),
|
||||
il_id: port_id,
|
||||
// TODO: CRIMES CRIMES CRIMES
|
||||
typ: Box::leak(Box::new(typ)),
|
||||
};
|
||||
ctx.signals
|
||||
.insert(port.net.name.fragment().to_string(), signal);
|
||||
}
|
||||
let ret_id = module.make_genid("ret");
|
||||
module.add_wire(rtlil::Wire::new(
|
||||
ret_id.clone(),
|
||||
TODO_WIDTH,
|
||||
Some(rtlil::PortOption::Output(99)),
|
||||
));
|
||||
let out_sig = lower_expression(ctx, module, &pa_comb.expr)?;
|
||||
module.add_connection(&rtlil::SigSpec::Wire(ret_id), &out_sig);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
|
||||
let mut writer = rtlil::ILWriter::new();
|
||||
let mut ir_module = rtlil::Module::new(make_pubid("test"));
|
||||
|
||||
writer.write_line("autoidx 1");
|
||||
ir_module.write_rtlil(&mut writer);
|
||||
Ok(writer.finish())
|
||||
}
|
||||
|
|
@ -1,15 +1,22 @@
|
|||
use super::types::Type;
|
||||
use super::{types::Type, Context};
|
||||
|
||||
/// an abstract element that performs some kind of computation on a value
|
||||
struct Element<'ty> {
|
||||
/// an abstract element that performs some kind of computation on inputs
|
||||
#[derive(Debug)]
|
||||
pub struct Expr<'ty> {
|
||||
pub id: u32,
|
||||
pub inputs: Vec<Element<'ty>>,
|
||||
pub inputs: Vec<Expr<'ty>>,
|
||||
pub typ: Type<'ty>,
|
||||
}
|
||||
|
||||
struct Signal<'ty> {
|
||||
#[derive(Debug)]
|
||||
pub struct Signal<'ty> {
|
||||
pub id: u32,
|
||||
pub typ: Type<'ty>,
|
||||
}
|
||||
|
||||
struct Expression {}
|
||||
/// A block of HDL code, e.g. comb block
|
||||
#[derive(Debug)]
|
||||
pub struct Block<'ty> {
|
||||
pub signals: Vec<Signal<'ty>>,
|
||||
pub expr: Expr<'ty>,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ pub struct TypeStruct<'ty> {
|
|||
kind: TypeKind<'ty>,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
enum TypeKind<'ty> {
|
||||
/// Elaboration-time types
|
||||
ElabType(ElabKind),
|
||||
|
|
@ -18,11 +19,13 @@ enum TypeKind<'ty> {
|
|||
Callable,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
struct ElabData<'ty> {
|
||||
typ: Type<'ty>,
|
||||
value: ElabValue<'ty>,
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
enum ElabValue<'ty> {
|
||||
/// the value is not given and has to be inferred
|
||||
Infer,
|
||||
|
|
@ -30,12 +33,14 @@ enum ElabValue<'ty> {
|
|||
Concrete(ElabValueData<'ty>),
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
enum ElabValueData<'ty> {
|
||||
U32(u32),
|
||||
Bytes(&'ty [u8]),
|
||||
}
|
||||
|
||||
/// Types that are only valid during Elaboration
|
||||
#[derive(Debug)]
|
||||
enum ElabKind {
|
||||
/// general, unsized number type
|
||||
Num,
|
||||
|
|
@ -90,6 +95,24 @@ impl<'ty> TypeStruct<'ty> {
|
|||
}
|
||||
}
|
||||
|
||||
impl std::fmt::Debug for TypeStruct<'_> {
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
|
||||
match &self.kind {
|
||||
TypeKind::Logic(width) => {
|
||||
if let Some(num) = width.try_u32() {
|
||||
write!(f, "Logic<{}>", num)
|
||||
} else {
|
||||
write!(f, "Logic<?>")
|
||||
}
|
||||
}
|
||||
_ => f
|
||||
.debug_struct("TypeStruct")
|
||||
.field("kind", &self.kind)
|
||||
.finish(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Helper functions to create primitive elaboration values
|
||||
impl<'ty> ElabData<'ty> {
|
||||
/// an integer
|
||||
|
|
@ -105,9 +128,12 @@ impl<'ty> ElabData<'ty> {
|
|||
/// return Some(u32) if this is a number
|
||||
pub fn try_u32(&self) -> Option<u32> {
|
||||
// TODO: assert this is actually a number
|
||||
match self.value {
|
||||
match &self.value {
|
||||
ElabValue::Infer => None,
|
||||
ElabValue::Concrete(_) => todo!(),
|
||||
ElabValue::Concrete(val) => match val {
|
||||
ElabValueData::U32(num) => Some(*num),
|
||||
ElabValueData::Bytes(_) => todo!(),
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -58,7 +58,12 @@ fn main() {
|
|||
if opt.debug {
|
||||
println!("{:#?}", res);
|
||||
}
|
||||
let lowered = crate::frontend::lower_module(res.1);
|
||||
let mut frontendcontext = crate::frontend::Context::new();
|
||||
let typed = frontendcontext.type_module(res.1);
|
||||
if opt.debug {
|
||||
println!("{:#?}", typed);
|
||||
}
|
||||
/*
|
||||
match lowered {
|
||||
Ok(res) => {
|
||||
let mut file = File::create(opt.output.unwrap_or_else(|| "out.rtlil".into()))
|
||||
|
|
@ -68,6 +73,7 @@ fn main() {
|
|||
}
|
||||
Err(err) => eprintln!("{:#?}", err),
|
||||
}
|
||||
*/
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue