move builting functions to own file
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33149eb5aa
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6abbd30792
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@ -0,0 +1,54 @@
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use crate::frontend::{Callable, CallArgument, Type};
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use crate::rtlil;
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fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell {
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\Y", y);
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cell
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}
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fn instantiate_binop(celltype: &str, id: &str, args: &[String], ret: &str) -> rtlil::Cell {
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let a = args.get(0).expect("wrong argcount slipped through type check");
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let b = args.get(1).expect("wrong argcount slipped through type check");
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\B_SIGNED", "0");
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cell.add_param("\\B_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\B", b);
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cell.add_connection("\\Y", ret);
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cell
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}
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fn make_binop_callable(name: &str, celltype: &'static str) -> Callable {
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let args = vec![
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CallArgument {
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name: "A".to_owned(),
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atype: Type::wire(),
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},
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CallArgument {
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name: "B".to_owned(),
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atype: Type::wire(),
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},
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];
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Callable {
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name: name.to_owned(),
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args,
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ret: Type::wire(),
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instantiate: Box::new(move |id, args, ret| instantiate_binop(celltype, id, args, ret))
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}
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}
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pub fn get_builtins() -> Vec<Callable> {
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vec![
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make_binop_callable("and", "$and"),
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make_binop_callable("xor", "$xor"),
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]
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}
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@ -1,30 +1,8 @@
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use std::collections::BTreeMap;
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use crate::parser;
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use crate::rtlil;
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fn builtin_binop_cell(celltype: &str, id: &str, a: &str, b: &str, y: &str) -> rtlil::Cell {
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\B_SIGNED", "0");
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cell.add_param("\\B_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\B", b);
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cell.add_connection("\\Y", y);
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cell
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}
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fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell {
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\Y", y);
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cell
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}
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// the hacky way
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use crate::builtin_cells::get_builtins;
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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@ -58,45 +36,46 @@ pub enum Type {
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Wire(GenericParam<u32>)
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}
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// module that can be instantiated like a function
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pub struct Callable {
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impl Type {
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pub fn wire() -> Self {
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Self::Wire(GenericParam::Unsolved)
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}
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}
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fn lower_expression(module: &mut rtlil::Module, expr: &parser::Expression) -> Result<String, CompileError> {
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pub struct CallArgument {
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pub name: String,
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pub atype: Type,
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}
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// module that can be instantiated like a function
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pub struct Callable {
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pub name: String,
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pub args: Vec<CallArgument>,
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pub ret: Type,
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pub instantiate: Box<dyn Fn(&str, &[String], &str) -> rtlil::Cell>
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}
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struct Context {
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callables: BTreeMap<String, Callable>
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}
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fn lower_expression(ctx: &Context, module: &mut rtlil::Module, expr: &parser::Expression) -> Result<String, CompileError> {
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match expr {
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parser::Expression::Ident(ident) => Ok(make_pubid(&ident)),
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parser::Expression::Call(call) => {
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let output_gen_id = module.make_genid("cell");
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module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None));
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let mut args_resolved = call.args.iter().map(|expr| lower_expression(module, expr));
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let args_resolved = call.args.iter()
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.map(|expr| lower_expression(ctx, module, expr)).collect::<Result<Vec<_>, _>>()?;
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// TODO: make this sensible
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let cell = match *call.name.fragment() {
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"and" => {
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let arg_a = args_resolved.next().unwrap()?;
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let arg_b = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("and");
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builtin_binop_cell("$and", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"xor" => {
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let arg_a = args_resolved.next().unwrap()?;
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let arg_b = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("xor");
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builtin_binop_cell("$xor", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"not" => {
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let arg_a = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("not");
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builtin_unop_cell("$not", &cell_id, &arg_a, &output_gen_id)
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}
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"reduce_or" => {
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let arg_a = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("reduce_or");
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builtin_unop_cell("$reduce_or", &cell_id, &arg_a, &output_gen_id)
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}
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name => return Err(CompileError::new(CompileErrorKind::UndefinedReference(name.to_owned()))),
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};
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let callable = ctx.callables.get(call.name.fragment() as &str).ok_or_else(|| {
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CompileError::new(CompileErrorKind::UndefinedReference(call.name.fragment().to_string()))
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})?;
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let cell_id = module.make_genid(&callable.name);
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let cell = (*callable.instantiate)(&cell_id, args_resolved.as_slice(), &output_gen_id);
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module.add_cell(cell);
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Ok(output_gen_id)
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}
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@ -104,9 +83,9 @@ fn lower_expression(module: &mut rtlil::Module, expr: &parser::Expression) -> Re
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}
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}
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fn lower_assignment(module: &mut rtlil::Module, assignment: parser::Assign) -> Result<(), CompileError> {
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fn lower_assignment(ctx: &Context, module: &mut rtlil::Module, assignment: parser::Assign) -> Result<(), CompileError> {
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let target_id = make_pubid(&assignment.lhs);
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let return_wire = lower_expression(module, &assignment.expr)?;
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let return_wire = lower_expression(ctx, module, &assignment.expr)?;
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module.add_connection(target_id, return_wire);
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Ok(())
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}
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@ -114,6 +93,7 @@ fn lower_assignment(module: &mut rtlil::Module, assignment: parser::Assign) -> R
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid(&pa_module.name));
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let mut context = Context { callables: get_builtins().into_iter().map(|clb| (clb.name.to_owned(), clb)).collect() };
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writer.write_line("autoidx 1");
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for (idx, port) in pa_module.ports.iter().enumerate() {
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let dir_option = match port.direction {
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@ -129,7 +109,7 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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}
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for stmt in pa_module.statements {
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match stmt {
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parser::Statement::Assign(assignment) => lower_assignment(&mut ir_module, assignment)?,
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parser::Statement::Assign(assignment) => lower_assignment(&context, &mut ir_module, assignment)?,
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}
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}
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ir_module.write_rtlil(&mut writer);
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