diff --git a/src/frontend.rs b/src/frontend.rs
index 4ef94e8..700d325 100644
--- a/src/frontend.rs
+++ b/src/frontend.rs
@@ -86,7 +86,7 @@ struct Context {
     /// map callable name to callable
     callables: BTreeMap<String, Callable>,
     /// map signal name to Signal
-    signals: BTreeMap<String, Signal>
+    signals: BTreeMap<String, Signal>,
 }
 
 impl Context {
@@ -95,8 +95,9 @@ impl Context {
     }
 
     fn try_get_signal(&self, signame: &str) -> Result<&Signal, CompileError> {
-        self.get_signal(signame)
-            .ok_or(CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned())))
+        self.get_signal(signame).ok_or_else(|| {
+            CompileError::new(CompileErrorKind::UndefinedReference(signame.to_owned()))
+        })
     }
 }
 
@@ -113,19 +114,17 @@ fn lower_process_statement(
             let next_sig;
             if let Some(sig) = pctx.next_sigs.get(assig.lhs) {
                 next_sig = sig.clone();
-            }
-            else {
+            } else {
                 let next_gen_id = format!("${}$next", assig.lhs);
                 module.add_wire(rtlil::Wire::new(&next_gen_id, TODO_WIDTH, None));
                 next_sig = rtlil::SigSpec::Wire(next_gen_id);
 
-                pctx.next_sigs.insert(assig.lhs.to_owned(), next_sig.clone());
+                pctx.next_sigs
+                    .insert(assig.lhs.to_owned(), next_sig.clone());
 
                 // trigger the modified value to update
-                pctx.updates.push((
-                    ctx.try_get_signal(assig.lhs)?.sigspec(),
-                    next_sig.clone(),
-                ));
+                pctx.updates
+                    .push((ctx.try_get_signal(assig.lhs)?.sigspec(), next_sig.clone()));
             };
 
             let next_expr_wire = lower_expression(ctx, module, &assig.expr)?;
@@ -198,15 +197,15 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
             let b = desugar_expression(b);
             parser::Call {
                 name: "and".into(),
-                args: vec![a, b]
+                args: vec![a, b],
             }
-        },
+        }
         parser::Operation::Or { a, b } => {
             let a = desugar_expression(a);
             let b = desugar_expression(b);
             parser::Call {
                 name: "or".into(),
-                args: vec![a, b]
+                args: vec![a, b],
             }
         }
         parser::Operation::Xor { a, b } => {
@@ -214,14 +213,14 @@ fn desugar_operation<'a>(op: parser::Operation<'a>) -> parser::Call<'a> {
             let b = desugar_expression(b);
             parser::Call {
                 name: "xor".into(),
-                args: vec![a, b]
+                args: vec![a, b],
             }
         }
         parser::Operation::Not(a) => {
             let a = desugar_expression(a);
             parser::Call {
                 name: "not".into(),
-                args: vec![a]
+                args: vec![a],
             }
         }
     }
@@ -236,10 +235,10 @@ fn desugar_expression<'a>(expr: parser::Expression<'a>) -> parser::Expression<'a
             let new_args = call.args.into_iter().map(desugar_expression).collect();
             call.args = new_args;
             parser::Expression::Call(call)
-        },
+        }
         parser::Expression::Operation(op) => {
             parser::Expression::Call(Box::new(desugar_operation(*op)))
-        },
+        }
     }
 }
 
@@ -253,7 +252,7 @@ fn lower_expression(
         parser::Expression::Ident(ident) => {
             let signal = ctx.try_get_signal(ident)?;
             Ok(signal.sigspec())
-        },
+        }
         parser::Expression::Call(call) => {
             let args_resolved = call
                 .args
@@ -321,9 +320,12 @@ pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
         let sig = Signal {
             name: port.net.name.to_owned(),
             il_id: make_pubid(port.net.name),
-            typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32))
+            typ: Type::Wire(GenericParam::Solved(port.net.width.unwrap_or(1) as u32)),
         };
-        let sig = context.signals.entry(port.net.name.to_owned()).or_insert(sig);
+        let sig = context
+            .signals
+            .entry(port.net.name.to_owned())
+            .or_insert(sig);
 
         let dir_option = match port.direction {
             parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
diff --git a/src/main.rs b/src/main.rs
index 7228e9f..ca40c1e 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -47,9 +47,11 @@ fn main() {
             let lowered = crate::frontend::lower_module(res.1);
             match lowered {
                 Ok(res) => {
-                    let mut file = File::create(opt.output.unwrap_or("out.rtlil".into())).expect("could not open file");
-                    file.write_all(res.as_bytes()).expect("failed to write output file");
-                },
+                    let mut file = File::create(opt.output.unwrap_or_else(|| "out.rtlil".into()))
+                        .expect("could not open file");
+                    file.write_all(res.as_bytes())
+                        .expect("failed to write output file");
+                }
                 Err(err) => eprintln!("{:#?}", err),
             }
         }