extract lowering into frontend
This commit is contained in:
NotAFile
parent
79e570dc60
commit
5b4f378526
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@ -0,0 +1,108 @@
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use crate::parser;
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use crate::rtlil;
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fn builtin_binop_cell(celltype: &str, id: &str, a: &str, b: &str, y: &str) -> rtlil::Cell {
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\B_SIGNED", "0");
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cell.add_param("\\B_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\B", b);
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cell.add_connection("\\Y", y);
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cell
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}
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fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> rtlil::Cell {
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let mut cell = rtlil::Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\Y", y);
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cell
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}
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// the hacky way
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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}
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#[derive(Debug)]
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pub struct CompileError;
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fn lower_expression(module: &mut rtlil::Module, expr: &parser::Expression) -> Result<String, CompileError> {
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match expr {
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parser::Expression::Ident(ident) => Ok(make_pubid(&ident)),
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parser::Expression::Call(call) => {
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let output_gen_id = module.make_genid("cell");
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module.add_wire(rtlil::Wire::new(&output_gen_id, 1, None));
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let mut args_resolved = call.args.iter().map(|expr| lower_expression(module, expr));
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// TODO: make this sensible
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let cell = match call.name.as_str() {
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"and" => {
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let arg_a = args_resolved.next().unwrap()?;
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let arg_b = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("and");
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builtin_binop_cell("$and", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"xor" => {
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let arg_a = args_resolved.next().unwrap()?;
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let arg_b = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("xor");
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builtin_binop_cell("$xor", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"not" => {
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let arg_a = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("not");
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builtin_unop_cell("$not", &cell_id, &arg_a, &output_gen_id)
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}
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"reduce_or" => {
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let arg_a = args_resolved.next().unwrap()?;
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let cell_id = module.make_genid("reduce_or");
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builtin_unop_cell("$reduce_or", &cell_id, &arg_a, &output_gen_id)
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}
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_ => return Err(CompileError {}),
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};
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module.add_cell(cell);
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Ok(output_gen_id)
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}
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parser::Expression::Operation(op) => todo!(),
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}
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}
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fn lower_assignment(module: &mut rtlil::Module, assignment: parser::Assign) -> Result<(), CompileError> {
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let target_id = make_pubid(&assignment.lhs);
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let return_wire = lower_expression(module, &assignment.expr)?;
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module.add_connection(target_id, return_wire);
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Ok(())
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}
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pub fn lower_module(pa_module: parser::Module) -> Result<String, CompileError> {
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let mut writer = rtlil::ILWriter::new();
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let mut ir_module = rtlil::Module::new(make_pubid(&pa_module.name));
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writer.write_line("autoidx 1");
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for (idx, port) in pa_module.ports.iter().enumerate() {
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let dir_option = match port.direction {
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parser::PortDirection::Input => rtlil::PortOption::Input(idx as i32 + 1),
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parser::PortDirection::Output => rtlil::PortOption::Output(idx as i32 + 1),
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};
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let wire = rtlil::Wire::new(
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make_pubid(&port.net.name),
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port.net.width.unwrap_or(1) as u32,
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Some(dir_option)
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);
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ir_module.add_wire(wire);
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}
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for stmt in pa_module.statements {
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match stmt {
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parser::Statement::Assign(assignment) => lower_assignment(&mut ir_module, assignment)?,
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}
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}
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ir_module.write_rtlil(&mut writer);
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Ok(writer.finish())
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}
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@ -1,6 +1,7 @@
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mod literals;
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mod parser;
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mod rtlil;
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mod frontend;
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use nom::error::convert_error;
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use std::fs::File;
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@ -34,8 +35,11 @@ fn main() {
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Err(_) => (),
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Ok(res) => {
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println!("{:#?}", res);
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let lowered = crate::rtlil::lower_module(res.1);
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println!("{}", lowered);
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let lowered = crate::frontend::lower_module(res.1);
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match lowered {
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Ok(res) => println!("{}", res),
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Err(err) => println!("{:#?}", err),
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}
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}
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}
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}
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168
src/rtlil.rs
168
src/rtlil.rs
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@ -1,6 +1,3 @@
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use crate::parser;
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use std::collections::HashMap;
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#[derive(Debug, Default)]
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pub struct ILWriter {
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data: String,
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@ -10,65 +7,71 @@ pub struct ILWriter {
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// this would be much nicer if indent gave you a new writer
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// which would indent things
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impl ILWriter {
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fn new() -> Self {
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pub fn new() -> Self {
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Default::default()
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}
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fn write_line(&mut self, line: &str) {
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pub fn write_line(&mut self, line: &str) {
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self.data += &"\t".repeat(self.indent);
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self.data += line;
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self.data += "\n";
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}
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fn indent(&mut self) {
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pub fn indent(&mut self) {
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self.indent += 1
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}
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fn dedent(&mut self) {
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pub fn dedent(&mut self) {
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self.indent = self
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.indent
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.checked_sub(1)
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.expect("tried to dedent negative amount")
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}
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fn finish(self) -> String {
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pub fn finish(self) -> String {
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self.data
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}
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}
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// the proper way
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#[derive(Debug)]
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pub enum WireOption {
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pub enum PortOption {
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Input(i32),
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Output(i32),
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Width(i32),
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}
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#[derive(Debug)]
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pub struct Wire {
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/// rtlil ID
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id: String,
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options: Vec<WireOption>,
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/// width in bits
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width: u32,
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/// Port info if this is a port
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port_info: Option<PortOption>
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}
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impl Wire {
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fn new(id: impl Into<String>) -> Self {
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pub fn new(id: impl Into<String>, width: u32, port_info: Option<PortOption>) -> Self {
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Wire {
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id: id.into(),
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options: Default::default(),
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width,
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port_info
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}
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}
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fn write_rtlil(&self, writer: &mut ILWriter) {
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let mut line = String::from("wire ");
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for option in &self.options {
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let option_str = match option {
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WireOption::Input(num) => format!("input {} ", num),
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WireOption::Output(num) => format!("output {} ", num),
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WireOption::Width(num) => format!("width {} ", num),
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if let Some(option) = &self.port_info {
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let port_str = match option {
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PortOption::Input(num) => format!("input {} ", num),
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PortOption::Output(num) => format!("output {} ", num),
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};
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line += &port_str;
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};
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line += &option_str;
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if self.width > 1 {
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line += &format!("width {} ", self.width);
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}
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line += &self.id;
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@ -77,7 +80,7 @@ impl Wire {
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}
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#[derive(Debug)]
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struct Module {
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pub struct Module {
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name: String,
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wires: Vec<Wire>,
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cells: Vec<Cell>,
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@ -86,7 +89,7 @@ struct Module {
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}
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impl Module {
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fn new(name: impl Into<String>) -> Self {
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pub fn new(name: impl Into<String>) -> Self {
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Module {
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name: name.into(),
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wires: Default::default(),
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@ -96,11 +99,19 @@ impl Module {
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}
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}
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fn add_wire(&mut self, wire: Wire) {
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pub fn add_wire(&mut self, wire: Wire) {
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self.wires.push(wire)
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}
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fn write_rtlil(&self, writer: &mut ILWriter) {
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pub fn add_connection(&mut self, target: String, source: String) {
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self.connections.push((target, source))
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}
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pub fn add_cell(&mut self, cell: Cell) {
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self.cells.push(cell)
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}
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pub fn write_rtlil(&self, writer: &mut ILWriter) {
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writer.write_line(&format!("module {}", self.name));
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writer.indent();
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for wire in &self.wires {
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@ -116,7 +127,7 @@ impl Module {
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writer.write_line("end");
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}
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fn make_genid(&mut self, stem: &str) -> String {
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pub fn make_genid(&mut self, stem: &str) -> String {
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let res = format!("${}${}", stem, self.gen_id);
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self.gen_id += 1;
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res
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@ -124,7 +135,7 @@ impl Module {
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}
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#[derive(Debug)]
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struct Cell {
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pub struct Cell {
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id: String,
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celltype: String,
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parameters: Vec<(String, String)>,
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@ -132,7 +143,7 @@ struct Cell {
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}
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impl Cell {
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fn new(id: &str, celltype: &str) -> Self {
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pub fn new(id: &str, celltype: &str) -> Self {
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Cell {
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id: id.into(),
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celltype: celltype.into(),
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@ -141,11 +152,11 @@ impl Cell {
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}
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}
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fn add_param(&mut self, name: &str, value: &str) {
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pub fn add_param(&mut self, name: &str, value: &str) {
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self.parameters.push((name.into(), value.into()))
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}
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fn add_connection(&mut self, from: &str, to: &str) {
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pub fn add_connection(&mut self, from: &str, to: &str) {
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self.connections.push((from.into(), to.into()))
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}
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@ -162,104 +173,3 @@ impl Cell {
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writer.write_line("end");
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}
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}
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fn builtin_binop_cell(celltype: &str, id: &str, a: &str, b: &str, y: &str) -> Cell {
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let mut cell = Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\B_SIGNED", "0");
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cell.add_param("\\B_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\B", b);
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cell.add_connection("\\Y", y);
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cell
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}
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fn builtin_unop_cell(celltype: &str, id: &str, a: &str, y: &str) -> Cell {
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let mut cell = Cell::new(id, celltype);
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cell.add_param("\\A_SIGNED", "0");
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cell.add_param("\\A_WIDTH", "1");
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cell.add_param("\\Y_WIDTH", "1");
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cell.add_connection("\\A", a);
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cell.add_connection("\\Y", y);
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cell
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}
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// the hacky way
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fn make_pubid(id: &str) -> String {
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"\\".to_owned() + id
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}
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fn lower_expression(module: &mut Module, expr: &parser::Expression) -> String {
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match expr {
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parser::Expression::Ident(ident) => make_pubid(&ident),
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parser::Expression::Call(call) => {
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let output_gen_id = module.make_genid("cell");
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module.add_wire(Wire::new(&output_gen_id));
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let mut args_resolved = call.args.iter().map(|expr| lower_expression(module, expr));
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// TODO: make this sensible
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let cell = match call.name.as_str() {
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"and" => {
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let arg_a = args_resolved.next().unwrap();
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let arg_b = args_resolved.next().unwrap();
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let cell_id = module.make_genid("and");
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builtin_binop_cell("$and", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"xor" => {
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let arg_a = args_resolved.next().unwrap();
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let arg_b = args_resolved.next().unwrap();
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let cell_id = module.make_genid("xor");
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builtin_binop_cell("$xor", &cell_id, &arg_a, &arg_b, &output_gen_id)
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}
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"not" => {
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let arg_a = args_resolved.next().unwrap();
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let cell_id = module.make_genid("not");
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builtin_unop_cell("$not", &cell_id, &arg_a, &output_gen_id)
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}
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"reduce_or" => {
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let arg_a = args_resolved.next().unwrap();
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let cell_id = module.make_genid("reduce_or");
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builtin_unop_cell("$reduce_or", &cell_id, &arg_a, &output_gen_id)
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}
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_ => todo!("unknown function"),
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};
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module.cells.push(cell);
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output_gen_id
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}
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parser::Expression::Operation(op) => todo!(),
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}
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}
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fn lower_assignment(module: &mut Module, assignment: parser::Assign) {
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let target_id = make_pubid(&assignment.lhs);
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let return_wire = lower_expression(module, &assignment.expr);
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module.connections.push((target_id, return_wire))
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}
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pub fn lower_module(pa_module: parser::Module) -> String {
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let mut writer = ILWriter::new();
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let mut ir_module = Module::new(format!("\\{}", pa_module.name));
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writer.write_line("autoidx 1");
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for (idx, port) in pa_module.ports.iter().enumerate() {
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let dir_option = match port.direction {
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parser::PortDirection::Input => WireOption::Input(idx as i32 + 1),
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parser::PortDirection::Output => WireOption::Output(idx as i32 + 1),
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};
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let wire = Wire {
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id: make_pubid(&port.net.name),
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options: vec![dir_option],
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};
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ir_module.wires.push(wire);
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}
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for stmt in pa_module.statements {
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match stmt {
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parser::Statement::Assign(assignment) => lower_assignment(&mut ir_module, assignment),
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}
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}
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ir_module.write_rtlil(&mut writer);
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writer.finish()
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}
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