diff --git a/src/frontend.rs b/src/frontend.rs
index b36e694..ca6589d 100644
--- a/src/frontend.rs
+++ b/src/frontend.rs
@@ -109,7 +109,7 @@ fn lower_assignment(
 ) -> Result<(), CompileError> {
     let target_id = make_pubid(assignment.lhs);
     let return_wire = lower_expression(ctx, module, &assignment.expr)?;
-    module.add_connection(target_id, return_wire);
+    module.add_connection(&target_id, &return_wire);
     Ok(())
 }
 
diff --git a/src/rtlil.rs b/src/rtlil.rs
index 8f8bb37..0107c72 100644
--- a/src/rtlil.rs
+++ b/src/rtlil.rs
@@ -46,6 +46,28 @@ pub trait RtlilWrite {
     fn write_rtlil(&self, writer: &mut ILWriter);
 }
 
+#[derive(Debug)]
+pub enum SigSpec {
+    Const(i32, u32),
+    Wire(String),
+}
+
+impl SigSpec {
+    pub fn wire(id: &str) -> Self {
+        Self::Wire(id.to_owned())
+    }
+}
+
+impl std::fmt::Display for SigSpec {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        match self {
+            SigSpec::Const(val, width) => write!(f, "{}'{}", width, val)?,
+            SigSpec::Wire(id) => write!(f, "{}", id)?,
+        };
+        Ok(())
+    }
+}
+
 #[derive(Debug)]
 pub struct Wire {
     /// rtlil ID
@@ -98,7 +120,7 @@ pub struct Module {
     name: String,
     wires: Vec<Wire>,
     cells: Vec<Cell>,
-    connections: Vec<(String, String)>,
+    connections: Vec<(SigSpec, SigSpec)>,
     gen_id: i32,
 }
 
@@ -117,8 +139,8 @@ impl Module {
         self.wires.push(wire)
     }
 
-    pub fn add_connection(&mut self, target: String, source: String) {
-        self.connections.push((target, source))
+    pub fn add_connection(&mut self, target: &str, source: &str) {
+        self.connections.push((SigSpec::wire(target), SigSpec::wire(source)))
     }
 
     pub fn add_cell(&mut self, cell: Cell) {
@@ -151,7 +173,7 @@ pub struct Cell {
     id: String,
     celltype: String,
     parameters: Vec<(String, String)>,
-    connections: Vec<(String, String)>,
+    connections: Vec<(SigSpec, SigSpec)>,
 }
 
 impl Cell {
@@ -169,7 +191,7 @@ impl Cell {
     }
 
     pub fn add_connection(&mut self, from: &str, to: &str) {
-        self.connections.push((from.into(), to.into()))
+        self.connections.push((SigSpec::wire(from), SigSpec::wire(to)))
     }
 }
 
diff --git a/src/rtlil/sync.rs b/src/rtlil/sync.rs
index 3f708c4..ff34991 100644
--- a/src/rtlil/sync.rs
+++ b/src/rtlil/sync.rs
@@ -1,4 +1,4 @@
-use crate::rtlil::RtlilWrite;
+use crate::rtlil::{RtlilWrite, SigSpec};
 
 pub struct Process {
     id: String,
@@ -7,7 +7,7 @@ pub struct Process {
 }
 
 pub struct CaseRule {
-    assign: Vec<(String, String)>,
+    assign: Vec<(SigSpec, SigSpec)>,
     switches: Vec<SwitchRule>,
 }
 
@@ -18,7 +18,7 @@ pub struct SwitchRule {
 
 pub struct SyncRule {
     cond: SyncCond,
-    assign: Vec<(String, String)>,
+    assign: Vec<(SigSpec, SigSpec)>,
 }
 
 pub enum SyncCond {