futilehdl/doc/examples/clockdiv.fut

module clockdiv_2 (
	input wire clk,
	input wire rst,
	output wire out_clk
) {
	proc (clk) {
		match (not(rst)) {
			0 => out_clk = 0,
			1 => out_clk = not(out_clk)
		}
	}
}