futilehdl/lib/builtins/main.hyd



comb reduce_or (
	a: Logic
	)
	-> Logic<1> {
	
}
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00

get examples semi-working again 2022-02-04 23:58:47 +00:00			`comb reduce_or (`
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00			`a: Logic`
			`)`
			`-> Logic<1> {`
add pretty printing for typed IR 2022-02-15 22:56:52 +00:00
start reworking syntax for stdlib 2022-01-23 23:10:09 +00:00			`}`