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6148c599b8
futilehdl
/
lib
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builtins
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main.hyd
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start reworking syntax for stdlib
2022-01-23 23:10:09 +00:00
get examples semi-working again
2022-02-04 23:58:47 +00:00
comb reduce_or (
start reworking syntax for stdlib
2022-01-23 23:10:09 +00:00
a: Logic
)
-> Logic<1> {
}